JPS6194169A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To improve the memory access efficiency of the whole of a device by providing two memory busses for one memory and connecting processors, between which information is transferred much, to the same bus. CONSTITUTION:Processors 11 and 12 are connected to a memory bus 31, and processors 13 and 14 are connected to a memory bus 32. Bus use right control circuits 61 and 62 control the use right of memory busses 31 and 32 and are connected to processors 11, 12, 13, and 14 and a bus switch circuit 5. The bus switch circuit 5 separates and connects memory busses 31 and 32 logically to switch information transfer between processors 11-14 and a memory 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system in which a plurality of processors are connected to a set of memories.

[Prior art]

In a conventional multiprocessor system, multiple processors that basically share memory are connected to the same memory bus. FIG. 2 is an example of this, in which the processor 11
171 are connected to the memory bus 31, indicating that each processor shares the memory 2].

Nowadays, in devices such as communication control equipment, which have many interactions among each control, such as interface control with the processor to the upper host 1, interface control with the lower line, and control of internal transmission control procedures, the throughput is Consider the case where the multiprocessor system shown in FIG. 2 is applied to realize the following. Note that the processor 11
It is assumed that a host processor is connected to the , and a line is connected to the processor 14 . In this case, memory bus 3
1 is used when each processor 11-14 accesses memory 21, when transferring host 1 control information between processors 11 and 12, and when transferring line control information between processors 13 and 14.

Since the processing of processors 11.14 is strictly real-time, the bus usage priority is given to processors 12.14.
It needs to be higher than 13. Therefore, especially M (mega)
When a high-speed line on the bit/second order is accommodated, the memory bus usage rate for communication between processors that transfers host control and line control information becomes high, and memory access of processors 12 and 13 that perform transmission control processing increases. I was made to wait.

As a result, there is a problem in that the average instruction execution time of the processors 12 and 13 increases, and the throughput of the entire device decreases.

To solve this problem, as shown in FIG. 3, a dedicated interprocessor communication bus 41.・12a! One possible solution is to increase the amount of hardware, but it has the drawback of significantly increasing the amount of hardware required.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessor system that enables memory access and communication between processors simultaneously within the device, thereby improving the throughput of the entire device, without requiring a significant increase in the amount of hardware. .

[Structure of the invention]

The present invention provides two sets of memory buses 'C+17-' for one memory.
The memory buses are connected by a switch circuit, and while one memory bus is transferring information between processors connected to the bus, the other memory bus can access memory, and the switch circuit This enables information transfer between processors connected to both memory buses via the memory bus 5.

[Embodiments of the invention]

FIG. 1 shows a block diagram of one embodiment of the invention.

In FIG. 1, the memory 21 has two sets of access ports, a memory bus 32 is connected to one access port, and a memory bus 32 is connected to the other access port. The 9-car memory buses 31 and 32 are arbitrarily divided by the bus switch circuit 5.

It is now possible to combine. Processors 11, 12 are connected to memory bus 31, and processors 13, 14 are connected to memory bus 32. Bus right control circuit 6
1 controls the use of the memory bus 31;
Processor 11.12゜bus switch circuit 5 and signal line 1
11. A banquet was held on '121.51. Signal line 11
1.1'21 is the memory bus 31 of the processor 11.12
The usage right request/grant signal line 51 is the processor 1
3 or 111 communicates with the processor 11 or 12.

The bus right control circuit 62 controls the right to use the memory bus 32, and is connected to the processor 13.14° hash switch circuit 5 through signal lines 131, 141.52. (A frame 131.141 indicates processor 13.14
memory bus 32 usage right request/permission signal line, signal line 5
2, processor 11 or 12 is processor 13 or 14
This is a request/permission signal line for the right to use the memory bus 32 when communicating with the memory bus 32.

The operation of FIG. 1 is as follows. For example, processor 11
sends a request for the right to use the bus 31 via the signal line 111 to the control circuit 6■ in order to access the memory 21, the control circuit 61 checks the signal line 121.51 and 1. If there is no request for the right to use the bus from the processor 12 or the bus switch circuit 5, the right to use the bus 31 is given to the processor 11.

When a memory access request from the processor 11 arrives at the memory 21 via the bus 31, the memory 21 checks for an access request from the bus 32 side and 7. If not, processor 1
1 request is serviced. Similarly, when the processor 11 sends information to the processor 12, the right to use the bus 31 is secured under the control of the control circuit 61, and the information is sent to the processor 12.

When the processor 11 sends information to the processor 13, for example, it first secures the right to use the bus 31 under the control of the control circuit 61, and then sends the information to the bus switch circuit 5. When the bus switch circuit 5 receives this information, it recognizes that it is a request for the right to use the bus 32 from the bus 31 side, and issues a request for the right to use the bus 32 to the control circuit 62 via the signal line 52. . The control circuit 62 has a signal line 131.1=+1
Check the bus usage from processor 13.14 (
If there is no request, the bus switch circuit 5 is notified so that the right to use the bus 32 is given to the bus 31 side.

The lot switch circuit 5 receives the notification from the control circuit 62 and transmits the information on the bus 31 to the bus 32 side.

The operations on the processors 13 and 14 side are also similar to the above. Note that, when there are requests for the number S1, the memory 21 and the control circuits 61 and 62 select one usage right in a predetermined priority order Wc.

Further, the bus switch circuit 5 logically separates the bus 31 and the bus 32 when there is no request for communication between the buses, so for example, when the processors 11 and 12 are communicating via the bus 31, the 1'l can access the memory 21 via the bus 32;

In this embodiment, information transfer from the processor 11 to the processor 12 or 13 has been described.

By controlling the information transfer direction of the bus switch circuit 5, the processor 11 can easily read information from the processor 12 or 13.

C'g! Effects of Brightness] As explained above, according to the present invention, two sets of memory buses can be provided in one memory. By connecting two processors to the same bus, even when one bus is transferring information between processors, processors under the other bus cannot access memory. Therefore, the memory access efficiency of the entire device can be improved, which has the advantage of helping to improve the performance of the device.

The present invention requires a bus switch circuit, a bus right control circuit, etc., but these can be easily realized using LSI.
Compared to connecting processors using a dedicated bus, there is not much increase in hardware and the device does not become large-scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a memory bus configuration of a conventional multiprocessor system, and FIG. 3 is a diagram illustrating an improvement plan for the conventional memory bus configuration. . 11-14... Processor 21... Memory. 31.32...Memory bus, 5...Bus switch circuit, 61.62...Bus usage right control circuit.

Claims (1)

[Claims] (1) A memory, and two devices each independently connected to the memory.
a set of memory buses, one or more first processors connected to one memory bus, and one or more second processors connected to the other memory bus;
a bus switch circuit that logically separates and connects the one memory bus and the other memory bus; and a control that controls the right of the first or second processor and the bus switch circuit to use the one or the other memory bus. A multiprocessor system characterized by comprising a circuit.