JPS60196866A - Data processor - Google Patents

Abstract

PURPOSE:To attain parallel processing of data and high throughput by forming a bus to be used for accessing data to be processed by each processor independently in each processor. CONSTITUTION:A control processor 18 connects a buffer memory 25 to a memory access bus 40 by a bus connecting switch 47-1 and disconnects a buffer memory 28 from both the memory access bus 40 and a packet transfer bus 39. Receiving a packet, a circuit interface 45 informs the reception to an execution processor 19, which transfers the received packet to the buffer memory 25 and informs the transfer to the control processor 18. Receiving the information, the control processor 18 separates the buffer memory 25 from the memory access bus 40, connects the buffer memory 25 to a packet transfer bus 38 and a buffer memory 26 to a packet transfer bus 28 simultaneously and then outputs a command to a DMA controller 43 to transfer a packet to be processed from the buffer memory 25 to the buffer memory 26.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing device, and more particularly to a data processing device that can achieve high throughput using a multiprocessor system.

[Background of the invention]

For example, packet switching technology developed for data communications has recently been applied to facsimiles, etc., and as the scope of services expands, further improvements in packet throughput are expected.

Here, the configuration of a conventional packet switch will be explained using the drawings.

FIG. 1 shows the hardware configuration of a conventional packet switching system that stores and exchanges facsimile packets and the like. In this configuration, a plurality of modules 2 and 9 surrounded by dashed lines are connected to the bus 1 by bus adapters 5 and 6 to form a system.

For example, a packet received from the line 17-6 in the module 9 is received into a buffer in the memory (MM) 8 via the line interface 16, and after being processed by the CPU 7 (for example, a microprocessor), It is sent out again to another line via the line interface 14 or 15.

If storage and exchange such as facsimile is required, the data is transmitted to the memory 4 via the bus 1 by the bus adapter 6 and further via the bus adapter 5. Here, after being processed by the CPU 3, it is written to the disk 12 by the disk controller 11. When the data is read from the disk 12 and transmitted to another location, the reverse route is taken.

In the conventional packet switch configuration as described above, the processing throughput of one module is equal to the CP of each module.
Determined by U's ability. Therefore, line 17-1
~ If the speed of 17-6 increases and a larger value is required as the throughput of module 9, the CP
It will be necessary to increase the ability of U7.

In such a case, since the capability of one processor is limited, it is necessary to have a multiple processor configuration. For example, the line interfaces 14 to 16 may also have processors, and the processors may share part of the functions of the CPU 7, thereby decentralizing the functions, or processor to bus 13
One possible method is to add this to the system to distribute the load.

However, these methods have the following problems. That is, in the former method, there is a problem that the packet throughput is determined by the processing capacity of the processor provided in the line interface, and in the latter method, the packet throughput is determined by the processing capacity of the processor provided in the line interface.
There was a problem that control was difficult.

The above-mentioned problems apply not only to the packet switching equipment mentioned as an example, but also to other data processing devices.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in conventional data processing devices and to easily realize high throughput.
An object of the present invention is to provide a multiprocessor type data processing device.

[Summary of the invention]

The above-mentioned object of the present invention is to provide a data processing device having a processor, a memory, a bus, and an input/output interface, a memory access bus for a plurality of processors, an inter-buffer transfer bus independent of the memory access bus, and a data processing device for the plurality of processors. a plurality of buffer memories corresponding to the above, a bus changeover switch for connecting the plurality of buffer memories to the memory access bus or the inter-buffer transfer bus, a DMA controller and bus exchange for performing DMA transfer via the inter-buffer transfer bus; A data processing apparatus characterized in that a management processor is provided and a bus through which each processor accesses data to be processed is made independent for each processor, thereby enabling parallel processing of data.

will be accomplished.

[Embodiments of the invention]

EMBODIMENT OF THE INVENTION Hereinafter, after a detailed description of the present invention, embodiments will be described in detail based on the drawings.

FIG. 2 is a block diagram for explaining the present invention in detail. In the figure, 18 is a management processor, 19 to 21 are execution processors, and 22 to 24 are the execution processors 19.
-21 main memories are shown, 25-30 are buffer memories corresponding to the execution processors 19-21, 45 and 46 are line interfaces, and 48 is a management processor bus.

The execution processors 19 to 21 have a function of processing each packet under the control of the management processor 18. Each of the buffer memories 25 to 30 has a function of storing a packet to be processed. Also,
The buffer memories 25-30 are connected to a bus connection switch 47-
1 to 47-6, respectively, the memory access bus 4
0 to 42, a state connected to the packet transfer bus 38 or 39, and a state not connected to any of them.

Control of switching the connection of the buffer memories 25 to 30 is performed by the management processor 18 via signal lines 31 to 36. Further, packet transfer between the respective buffer memories is performed by DMA controllers (DMAC) 43 and 44 under the control of the management processor 18. Note that the programs of each execution processor are stored in the memory 2.
It is placed between 2 and 24.

The operation of this embodiment configured as described above will be explained below.

This will be explained with reference to the flowcharts of FIGS. 3 and 4. Note that FIG. 3 shows the processing procedure of the management processor 18, and FIG. 4 shows the processing classes of the execution processors 19 to 21, and (11) to (1) at the end of each operation description below.
5) each step of the processing of the management processor 18, (2)
1) to (24) indicate each step of processing by the execution processor.

The management processor 18 first connects the bus connection switch 47-
1 connects the buffer memory 25 to the memory access bus 40.
Further, the buffer memory 28 is not connected to either the memory access bus 40 or the packet transfer bus 39 (11, 12).

When the line interface 45 receives the packet, it notifies the execution processor 19 of this fact. execution processor 1
9 transfers the received packet to the buffer memory 25 and communicates it to the management processor 18 via the signal line 31 (21-24).

Management processor 18 controls bus connection switch 47-1 to disconnect buffer memory 25 from memory access bus 40 and connect it to packet transfer bus 38.

It also controls the bus connection switch 47-4 to connect the buffer memory 28 to the memory access bus 4o, and then instructs the execution processor 19 to perform the next packet reception process (13.14).

Furthermore, the management processor 18 connects the bus connection switch 47-2.
to control the buffer memory 26 and the packet transfer bus 38
and instructs the DMA controller 43 to transfer the bucket 1- to be processed from the buffer memory 25 to the buffer memory 26 (15). DMA controller 43
When the DMA transfer is completed, the management processor 1
Contact 8.

The management processor 18 controls the bus connection switch 47-2 to disconnect the buffer memory 26 from the packet transfer bus 38 and connect it to the memory access bus 41, and instructs the execution processor 20 to perform the corresponding process (12, 1).
3. '14). The execution processor 2o executes the corresponding process, and when the process is completed, notifies the management processor 18 to that effect (23.24).

The management processor 18 controls the bus connection switch 47-2 to disconnect the buffer memory 26 from the memory access bus 41 and connect it to the packet transfer bus 38, and also connects the buffer memory 27 and the packet transfer bus to DM.
The A controller 43 is activated to transfer the packet from the buffer memory 26 to the buffer memory 27 (15).

When the packet transfer is completed, the DMA controller 43 notifies the management processor 18 of this fact.

As a result, the management processor 18
7-3, disconnects the buffer memory 27 from the packet transfer bus 38 and connects it to the memory access bus 42,
The execution processor 21 is commanded to execute the corresponding process (12.13.14). The execution processor 21 performs appropriate processing on the packets in the buffer memory 27, and if necessary, executes transmission via the line interface 46 (23.24).

In the above explanation, in order to simplify the explanation, the packets have been described as one packet, but in reality, the packets are also processed through the buffer memories 2B and 29.30. Further, a plurality of packets may exist in each of the buffer memories at the same time, and the processing and transfer of these packets are controlled by the management processor 18.

In addition, in the above explanation, the memory access bus is
Although the case where there are two sets of packet transfer buses has been shown, there may be any number of sets of these buses.

Furthermore, in the above explanation, an example was shown in which the packets to be processed are transferred from left to right in FIG. In this case, the packet transfer bus may be divided into one for transferring from right to left and one for transferring from left to right.

In addition, in the process of returning the above-mentioned response, it is necessary for the execution processor to notify the management processor of this fact, and the management processor controls the DMA controller accordingly.

FIG. 5 shows an embodiment in which the present invention is applied to module 2 in the packet switch shown in FIG.

In the figure, symbols 4, 5.11 and 12 indicate the same components as shown in FIG.
8 indicates the same components as shown in FIG. 2, and IO indicates a system bus.

In this embodiment, the CPU 3 shown in FIG. 1 is replaced with a bus-switchable multi-microprocessor shown in FIG. Further, in this embodiment, an example is shown in which the bus-swappable multi-microprocessor is composed of three boards, and the memory access buses 40 and 42 are connected to the system bus IO, and the bus adapter 5 and the disk It transmits and receives packets to and from the controller 11.

It goes without saying that the present invention can also be applied to the module 9 shown in FIG. 1 in the same manner as described above. Furthermore, in the above explanation, the present invention has been explained using a packet switch as an example, but the present invention is not limited to the packet switch, but can be applied to a wide range of general data processing devices. Needless to say.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a processor.

A data processing device having a memory access bus and an input/output interface, a memory access bus for a plurality of processors, an inter-buffer transfer bus independent of the memory access bus, and a plurality of buffer memories corresponding to the plurality of processors; A bus changeover switch that connects the plurality of buffer memories to the memory access bus or the inter-buffer transfer bus, and a DMA controller and bus exchange management processor that perform DMA transfer via the inter-buffer transfer bus are provided so that each processor is Since the bus for accessing processing data is made independent for each processor, it has the remarkable effect of realizing a multiprocessor type data processing device that can perform parallel processing of data and easily achieve high throughput. be.

[Brief explanation of the drawing]

The first rEJ is a processing flowchart 1 showing a configuration example of a conventional packet switch, and FIG. 5 is an implementation of the present invention."25
~30: Buffer memory, 38, 39: Packet transfer bus, 40~42 = Memory access bus, 43, 44: D
MAC148: Management processor bus. □□□31 Refreshing 4-■

Claims (1)

[Claims] (1) In a data processing device having a processor, a memory, a bus, and an input/output interface, a memory access bus by a plurality of processors, an inter-buffer transfer bus independent of the memory access bus, and a buffer-to-buffer transfer bus corresponding to the plurality of processors. A plurality of papua memories, a bus changeover switch for connecting the plurality of papua memories to the memory access bus or the inter-buffer transfer bus, and a DMA controller and a bus exchange management processor for performing DMA transfer via the inter-buffer transfer bus, A data processing device characterized by being capable of parallel processing of data.