JPS5748150A - Common memory control system - Google Patents

Common memory control system

Info

Publication number
JPS5748150A
JPS5748150A JP12189880A JP12189880A JPS5748150A JP S5748150 A JPS5748150 A JP S5748150A JP 12189880 A JP12189880 A JP 12189880A JP 12189880 A JP12189880 A JP 12189880A JP S5748150 A JPS5748150 A JP S5748150A
Authority
JP
Japan
Prior art keywords
signal
circuit
bus
access request
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12189880A
Other languages
Japanese (ja)
Inventor
Tomoyoshi Fukushima
Shuji Miki
Kazuyuki Masuo
Toshihiko Nihei
Katsuhiko Yazawa
Yoshiharu Iwamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP12189880A priority Critical patent/JPS5748150A/en
Publication of JPS5748150A publication Critical patent/JPS5748150A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To shorten the bus length and to reduce the bus delay, by dividing plural processors into plural groups, connecting the respective processors to a common bus, selecting an access request from the processor in the group, and accessing a memory circuit. CONSTITUTION:Selecting circuits SLo-SLm select an access request signal rq from a processor in each group #o-#m, output a bsy signal busy, and also send out a response signal and to a processor which has received the access request. Also, a selecting circuit SL selects the signal bsy from the circuits SLo-SLm of the respective interface circuits INFo-INFm in the same way as the concurrent selection of the access request signal, sends out a response signal (an) to a bus interface circuit corresponding to the received signal bys, and also sends out a timing signal (t) for controlling the bus. A memory controlling circuit MC starts a memory circuit M when the signal (an) is sent out from the circuit SL.
JP12189880A 1980-09-03 1980-09-03 Common memory control system Pending JPS5748150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12189880A JPS5748150A (en) 1980-09-03 1980-09-03 Common memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12189880A JPS5748150A (en) 1980-09-03 1980-09-03 Common memory control system

Publications (1)

Publication Number Publication Date
JPS5748150A true JPS5748150A (en) 1982-03-19

Family

ID=14822631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12189880A Pending JPS5748150A (en) 1980-09-03 1980-09-03 Common memory control system

Country Status (1)

Country Link
JP (1) JPS5748150A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6194169A (en) * 1984-10-13 1986-05-13 Nippon Telegr & Teleph Corp <Ntt> Multiprocessor system
FR2664071A1 (en) * 1990-06-28 1992-01-03 Nec Corp Information processor with interface expansion adapter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6194169A (en) * 1984-10-13 1986-05-13 Nippon Telegr & Teleph Corp <Ntt> Multiprocessor system
FR2664071A1 (en) * 1990-06-28 1992-01-03 Nec Corp Information processor with interface expansion adapter

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