SU438990A1 - Device for sampling multiprocessor system commands - Google Patents

Description

one

The invention relates to the field of computing and is intended for use in asynchronous computing systems with multiple processors.

Devices used in computing systems are known in which each processor has access to its own memory blocks. In this case, it is possible to use the floor of commands of one memory block by several processors.

A disadvantage of the known devices is that in them the search for the next processor that submitted the service is performed only after the completion of the process of fetching the instruction from the memory, and the service time of each processor is the sum of the times of the retrieval of the next instruction and the retrieval of the instruction.

The aim of the invention is to reduce the service time of the processor stock, which makes it possible to increase the effective speed of the computing system.

SUMMARY OF THE INVENTION The essence of the invention is that a device has a memory occupation trigger, a processor number register, a control signal switch and a delay circuit, the input of which is connected to the second output of the comparison circuit, the second input of the memory block and the first input of the second circuit. the second input of which is connected to the second

output decoder. The third input of the second circuit “AND” is connected to the output of the memory trigger trigger, the first input of which is connected to the output of the delay circuit and to the first

the reset switch input, the second one with the output of the first OR circuit, the second input of which is connected to the second output of the memory unit and the first input of the control signal switch whose output is connected

to the output of the device. The output of the register number of the processor, the input of which is connected to the output of the second AND circuit, is connected to the second inputs of the switch of the command registers, the reset switch, the control switch

signals and to the input of the switch counters commands.

The drawing shows a diagram of the device for selecting commands.

The device contains a register for wok 1; “OR 2; scheme "And 3; generator 4; counter 5; decoder 6; comparison circuit 7; trigger 8; “OR 9; memory block 10; register number processor 11; scheme "And 12; memory 13 trigger; delay circuit

14; command counter switch 15; switch command registers 16; reset switch 17; control signal switch 18; command counters 19, 20; command registers 21, 22; memory bus 23,

memory response bus 24; the input is the start of the device reset device 25; input device requests 26 and device output 27. In the presence of at least one request in the register of the application 1, the signal from its output through the OR 2 circuit arrives at the input of the first AND 3 circuit, which in the open state passes the sequence of signals from the generator 4 to the counter 5. Using the decoder 6 and the circuit Comparison 7 determines the next bit of the register number 1, containing one. The trigger 8 is set to the zero position by the signal from the comparison circuit 7, closing the first circuit "AND 3 and thereby fixing in the counter 5 the number of the processor that sent the request to the register for wok 1. At the same time, the reference signal is removed from the comparison circuit 7 to the memory block 10. The trigger 8 can be returned to the single state through the circuit OR 9 either by the initial reset pulse applied to the device input 25 or by the response signal received on the slit 24 from the memory block 10 and signaling the end of the command sampling out of him. After completing the search for the next left single signal from the decimator 6, a pulse from the comparison circuit 7 opens the second circuit AND 12 and writes one into the corresponding register register 11 and simultaneously via the delay circuit 14 sets the memory uploader trigger 13 to the state corresponding to the second Circuits And 12. The signal from the register I sets the switches 15, 16 to the states corresponding to the connection of the desired command counter 19, 20 and the command register 21, 22 to the memory block 10. The same signal controls the switch 17, which installed Vaeth to the initial discharge state register requisition 1. The switch 17 is also controlled by a signal coming from the output of the comparison circuit 7 through a time interval provided by delay circuit 14 after recording into register 11 served by a processor number. The signal from the register And and the signal received on the bus 24 control the switch 18. From the output of the switch 18, a control signal is removed, which is fed from the output 27 of the device to the corresponding processor and ensures the execution of the selected command. The device allows the selection of instructions both sequentially across the processors, not giving preference to either of them (only the initial reset of counter 5 is performed) and the priority maintenance of the processors with resetting counter 5 after each service cycle to the position corresponding to the highest priority processor. In this case, an independent parallel selection of commands from the device memory block is provided. The subject of the invention. A device for selecting commands of a multiprocessor system, comprising instruction counters, instruction registers, instruction counter switches, instruction registers, reset, memory block, counter, decoder, comparison circuit, trigger, register, wok, AND and OR generator The output of which is connected via the first AND circuit to the first input of the counter, the second input of which is connected to the first input of the device and to the first input of the first OR circuit, the output of the counter is connected to the input of the decoder, the first output of which is connected to the first input for the comparison circuit, the first output of which is connected to the first trigger input, the second input of which is connected to the output of the first OR circuit, the trigger output is connected to the second input of the first AND circuit, the third input of which is connected via the second OR circuit to the first output of the register the second output of which is connected to the second input of the comparison circuit, the first and second inputs of the register of the order are connected respectively to the output of the reset switch and the second input of the device, the outputs of the command counters are connected to the switch through the switch of the program counters The memory input of the memory unit, the first output of which is connected to the first input of the switch of command registers, each output of which is connected to the input of the corresponding command register, is characterized in that, in order to reduce the service time of the processor order, a memory open trigger is inserted into it, the processor number register, the control signal switch and the delay circuit whose input is connected to the second output of the comparison circuit, the second input of the US and the first input of the second AND circuit, the second input of which is connected to the second The output of the de-embedder, the third input of the second circuit “AND” is connected to the output of the memory trigger, the first input of which is connected to the output of the delay circuit and the first input of the reset switch, the second - to the output of the first OR circuit, the second input of which is connected to the second output of the unit the memory and the first input of the switch of control signals, the output of which is connected to the output of the device; the output of the register of the processor number, the input of which is connected to the output of the second AND circuit, is connected to the second inputs of the switch of the command registers, the reset switch, the control signal switch and to the input of the switch of the command counters.