JPS61249142A - Interruption circuit - Google Patents

Abstract

PURPOSE:To perform interript processings independent of each other for the fall and the rise of an input signal by providing one interruption port and one interruption circuit. CONSTITUTION:An interruption request register 21 is sampled by a sampling signal SAMP1 and is set to '1' when an interruption request signal IRQSET is in the high level. The register 21 is reset to '0' by the generation of a reset signal of hardware or a sampling signal SAMP2 if an interruption signal INT1 or INT2 is in the high level. The register 21 can be set to '1' or '0' by the value of a data bus DB. An interrupt mask register 22 determines whether a generated interruption request should be enabled or disabled. The register 22 is set to '1' or '0' by the input from the data bus DB, and the interrupt request is enabled if the register 22 is set to '1', and the interruption request is disabled if the register 22 is set to '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an interrupt circuit in a microcomputer.

<Prior art> In a conventional interrupt circuit, an interrupt is generated at the falling and rising edges of an input signal to an interrupt port, and when separate interrupt processing is performed at the falling and rising edges of the input signal, the input Since an interrupt can only be generated on either the falling edge or rising edge of the signal, two interrupt ports are used, and the input signal is connected to one interrupt port, and the input signal is connected to the other interrupt port. was achieved by connecting the input signal through an inverter.

Is the above method one? Since two interrupt ports are used for input signals, the number of signal inputs for requesting interrupt processing is reduced. Also, two internal interrupt circuits are used to generate separate interrupt signals at the falling and rising edges of the input signal, but interrupts at the falling and rising edges of the input signal occur simultaneously. Since there is no problem, the efficiency of hardware usage is also low.

In addition, there are some devices that can be switched to generate an interrupt at the falling edge or the rising edge of the input signal by changing the mode setting, but in such devices, the software detects the input signal and handles separate interrupts. I was going.

The above method places a burden on the software. Furthermore, since the input signal is detected by software, there is a drawback that the interrupt processing time is slow.

<Objective of the Invention> The present invention solves the above-mentioned conventional drawbacks and enables separate interrupt processing at the falling edge and rising edge of an input signal using one interrupt port and one interrupt circuit.

<Example> Examples of the present invention will be given below and detailed explanation will be given.

A block diagram of the present invention is shown in FIG.

The input signal sample and edge detection circuit 1 in FIG.
The input signal 3 from the interrupt boat 2 is sampled using an internal clock, and the falling and rising edges of the input signal are detected to generate pulses.

An interrupt request and determination circuit 4 connected to the input signal sample and edge detection circuit 1 generates an interrupt request signal based on the pulses generated by the input signal sample and edge detection circuit 1. The interrupt request signal can be selected by the pulse enable signal line 5 to be generated only at the falling edge of the input signal 3, only at the rising edge, or at both the falling edge and the rising edge. The interrupt request and determination circuit 4 also has a function of determining whether the interrupt request signal is generated at the falling edge or the rising edge of the input signal 3.

The interrupt request register and interrupt mask register circuit 6 is composed of an interrupt request register and an interrupt mask register. The interrupt request register is set to "1" by the interrupt request signal, and the 0 interrupt mask register is masked by the interrupt mask register. “1”
If so, generate an interrupt enable signal.

The interrupt request and determination circuit 4 receives an interrupt enable signal generated from the interrupt request register and interrupt mask register circuit 6, and generates an interrupt signal according to the determined conditions.

The interrupt request and determination circuit 4 is also connected to a vector address generation section (not shown). This vector address generation section receives a plurality of interrupt signals generated from the interrupt request and determination circuit 4, detects the interrupt signal with the highest priority, and generates a vector address corresponding to the interrupt signal.

It also notifies a control unit (not shown) of the occurrence of an interrupt.

FIG. 2 shows a logic diagram of the input signal sample and edge detection circuit.

The input signal sample and edge detection circuit consists of two stages of 7 lip-flops 7 and 8, a Nant gate 9 and an OR gate 1.
Consists of 0. Input signal 3 is input to flip-flop 7
and 8, the signal is sampled by the internal clock CLKII, and synchronized with the falling edge of the internal clock CLKII. The outputs of flip-flops 7 and 8 are connected to the inputs of the Nant gate 9 and the OR gate 10, and outputs INHL and INLH as edge detection pulse signals (negative logic) at the falling and rising edges of the input signal 3, respectively. .

FIG. 3 shows a logic diagram of the interrupt request and determination circuit.

The interrupt request and determination circuit is composed of two NOR latches 12 and 13 and four NOR gates 14, 15, 16 and 17.

Pulse enable signals (negative logic) HLEN and LHEN and edge detection pulses INHL and INLH are applied to the inputs of the NOR gates 14 and 15, respectively.
8 and 19, and the signal IRQ from the interrupt request register is connected via MO8FE'f'20.

Pulse enable signals HLEN and LHEN enable the. This pulse enable signal selects whether to generate an interrupt when the interrupt boat input signal falls only, only when it rises, or both falls and rises.The signal IRQ from the interrupt request register is While the interrupt request register is set to "1", the edge detection pulse is input so as not to be accepted.

Note that the internal clock CL is connected to the gate input of the MOSFET.
K is connected to synchronize the edge detection pulse and signal IRQ from the interrupt request register with internal clock signal CLK.

NOR gates 14 and 15 generate an output upon receiving an edge detection pulse when enabled. Noah Gate 14 and 1
The output of 5 is connected to the SET input of Noah latch 12.
The output interrupt request signal I RQ S ET is set to “H”.
i gh”.The RESET input of the NOR latch 12 is connected to the RESET signal of the NOR latch 12 and the signal IRQ from the interrupt request register to the MO8FET2.
Connected via 0. Interrupt request signal I RQ
SET is set to “Low” by hardware reset or by setting the interrupt request register to “1”.
become.

The outputs of NOR gates 14 and 15 are also connected to NOR latch 13. The output of the NOR gate 14 is the NOR latch 13
The output of the NOR gate 15 is connected to the SET input of the NOR latch 13. Noah Latch 1
Step 3 determines whether the generated interrupt request occurred at the falling edge or rising edge of the input signal.

A positive logic output and a negative logic output of this NOR latch 13 are connected to inputs of NOR gates 16 and 17, respectively. Other inputs of the NOR gates 16 and 17 include an interrupt enable signal (negative logic) INTEN from an interrupt request register and an interrupt mask register circuit, and a priority signal (negative logic) PRI and a vector address generation circuit (not shown). PH1 are connected to each other.

This is to suppress the generation of interrupt signals 1NT1 and INT2 from this block when an interrupt request with a higher priority than that from the block is generated. If there is no interrupt request with higher priority than the interrupt request of this block, NOR gates 16 and 17
generates interrupt signals lNTl and INT2 as outputs.

Note that the interrupt signals lNTl and INT2 are not generated simultaneously; lNTl is generated as an interrupt signal at the falling edge of the input signal, and INT2 is generated as an interrupt signal on the rising edge of the input signal. The address generation unit (not shown) detects and generates a vector address corresponding to each interrupt signal, and notifies the control unit (not shown) that an interrupt has occurred. Figure 4 shows the interrupt request register and 1 shows a logic diagram of an interrupt mask register circuit.

This block is composed of an interrupt request register 21, an interrupt mask register 22, and a Nante gate 23.

The interrupt request register 21 receives an interrupt request signal I R
It is set to “1” by Q S ET, and the vector address is taken into the control unit (not shown), so that “
0”.

First, the interrupt request signal IRQSET is sampled by the first sampling signal SAMPI, and at this time, if the interrupt request signal IRQSET is "High", the interrupt request register 21 is set to "1". Resetting the interrupt request register 21 to “O#” is as follows:
This is done by sampling the interrupt signals INTl and INT2 using the RESET signal of hardware reset or the second sampling signal S AMP2. The second sampling signal SAMP2 is generated when the vector address is taken into a control section (not shown), and at this point, the interrupt signal lNTl or I
If NT2 is "High", the interrupt request register 21 is reset to "0". Also, the interrupt request register 21 is set to "1" or "1" depending on the value of the data bus DB.
It can also be set to '0#.

The interrupt mask register 22 determines whether to enable or disable a generated interrupt request. "1" or "θ"' of the interrupt mask register 22
Setting is performed by input from data bus DB. If set to 1'', the interrupt request is enabled, and if set to 0, it is disabled.

The input of the Nante gate 23 is the interrupt request register 2.
1 and the output of the interrupt mask register 22 are connected, and when both become "1", an interrupt enable signal (negative logic) INTEN is output.

Note that the circuit composed of MO8FETs 24, 25, 26 and 27 and the NOR gate 28 is connected to the interrupt request register 2.
1 or the state of the interrupt mask register 22 to the data bus DB.

The circuit example described above has a one-pit configuration, and if a circuit of several bits is required, the circuit described above may be configured for the required number of bits.

<Effects of the Invention> With the above circuit configuration, one interrupt circuit can detect falling and rising edges of an input signal and perform separate interrupt processing without burdening software.

[Brief explanation of drawings]

FIG. 1 is a system block diagram of the present invention, and FIG. 2 is a system block diagram of the present invention.
3 is a logic circuit diagram of the input signal sample and edge detection circuit shown in the figure, FIG. 3 is a logic circuit diagram of the interrupt request and determination circuit shown in FIG. A logic circuit diagram of a mask register circuit is shown. 1... Input signal sample and edge detection circuit, 2...
・Interrupt board, 3...Interrupt request input signal, 4
... Interrupt request and judgment circuit, 5... Pulse enable signal line, 6... Interrupt request register and interrupt mask register circuit, 7, 8... Input signal sampling request latch, 13... Interrupt judgment Latch, 14.
15... Edge pulse transmission game), 16.17...
・Interrupt signal output gate, 21... Interrupt request register, 22... Interrupt mask register, 23...
・Interrupt enable signal output gate. Agent Patent attorney Aihiko Fukushi (and 2 others) Figure 1

Claims (1)

[Claims] 1. In an interrupt circuit of a microcomputer, a first means detects falling and rising edges of an input signal of an interrupt port and generates a pulse, and receives a pulse generated from the first means and generates an interrupt request signal. an interrupt request register that is set by the interrupt request signal generated by the second means; and an interrupt mask register that masks the interrupt request register and controls output of the interrupt enable signal; The second means has a function of determining whether the interrupt request signal outputted from the second means is generated at a falling edge or a rising edge of the input signal, and the two interrupt signals are controlled by the interrupt enable signal. and third means for generating an interrupt.