JPH05113903A - Address coincidence detecting circuit - Google Patents

Abstract

PURPOSE:To report the detection of the coincidence of addresses when an event showing the designated address coincidence event generating frequency occurs or an event exceeding said event generating frequency occurs. CONSTITUTION:A comparator 3 compares the address stored in an address register 1 with the value of a comparison address register 2. Then the comparator 3 outputs a comparison signal 4 when the coincidence is confirmed through the comparison. An address coincidence signal generating circuit 7 compares the value of a frequency designating register 6 with the output of a counter circuit 5 after the signals 4 are counted by the circuit 5. Then a coincidence signal 8 is outputted when the coincidence is confirmed through the comparison of the circuit 7. At the same time, a flip-flop 9 is set. If a mode register 10 is set in a mode where the OR is secured between both signals 4 and 8, the detection of address coincidence is reported every time an event occurs thereafter (signal 4 is valid).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION Address coincidence detection circuit of the present invention,
In particular, the present invention relates to an address match detection circuit for a main memory address or a microprogram address in debugging an information processing device.

[0002]

2. Description of the Related Art A conventional address match detection circuit of this type is a bus trace circuit, a microprogram execution trace circuit, an address at the time of main memory access (hereinafter simply referred to as main memory address) or a microprogram execution address ( Below, simply referred to as a micro address) and the address at the time of the target event (hereinafter referred to as comparison address) are compared. If the results match, after the end of the software instruction being executed, or the execution of the micro program instruction. By generating an interrupt or the like after the end, the occurrence of a target event is detected.

[0003]

In this conventional address match detection circuit, when a match between the main memory address or the micro address and the comparison address is detected, an address match signal is directly output to report the occurrence of the event. .. However, the target event may not always be the event at the time of the first address match. Therefore, the occurrence of an event is reported many times before the occurrence of the intended event, so that there is a problem that the efficiency at the time of evaluation or failure analysis is low.

[0004]

SUMMARY OF THE INVENTION The circuit of the present invention comprises an address register for storing a main memory address or a microprogram address in an address coincidence detection circuit which is one means for evaluating or fault analysis of an information processing device,
A comparison address register that stores an address to be compared with the main memory address or the microprogram address, a comparison circuit that outputs a comparison signal when the comparison results in a match, a count circuit that counts the comparison signal, and the comparison It is characterized by comprising a number-of-times designation register for designating the number of times of signal generation, and an address-match signal generation circuit for generating an address-match signal when the output of the count circuit and the value of the number-of-times register match.

[0005]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

In FIG. 1, reference numeral 1 is an address register for storing a main memory address or a micro address, and which address is to be stored is arbitrary. 2 is a comparison address register for storing an address to be compared with the main memory address or the micro address when an event occurs,
Reference numeral 3 is a comparison circuit for comparing the addresses stored in the address register 1 and the comparison address register 2, and validates the comparison signal 4 when the comparison results match.

Reference numeral 5 is a count circuit for counting the comparison signal 4, 6 is a count designation register for designating the number of counts of the count circuit 5, and 7 is an address match when the output of the count circuit 5 and the value of the count designation register 6 match. This is an address coincidence signal generation circuit for generating the signal 8 and further setting the flip-flop 9.

Reference numeral 10 is a mode register for designating whether or not the comparison signal 4 is logically ORed with the address coincidence signal 8 when the flip-flop 9 is set, 11 is an AND gate,
Reference numeral 12 is an OR gate, and reference numeral 13 is an address match report signal for reporting address match.

Next, the operation of the present invention will be described.

At the time of evaluation or failure analysis, the main memory address at the time of event occurrence, ie, the micro address, is set in the comparison address register 2, and the target event is at what time of event occurrence or at what time of event occurrence. The number of times is set in the number-of-times designation register 6 depending on whether the subsequent event occurs. Further, if necessary, the count circuit 5 and the flip-flop 9 are initialized and values are set in the mode register 10.

Next, execution of software instructions and the like is started. Now, assuming that the address match is detected by the main memory address, the main memory address is set in the address register 1 at the time of accessing the main memory, and is compared with the comparison address register 2 in the comparison circuit 3. If the comparison result is a match, the comparison signal 4 becomes valid, is input to the counting circuit 5, and is counted.

Then, the address match signal generation circuit 7 compares the count circuit 5 with the number of times designation register 6,
When the count circuit 5 counts the number of times set in the number-of-times specifying register 6, the address match signal 8 becomes valid, and at the same time, the flip-flop 9 is set.

The address match signal 8 becomes an address match report signal 13 via the OR gate 12. Then, when the mode register 10 is set to logically add the comparison signal 4 to the address coincidence signal, the comparison signal 4 and the value of the flip-flop 9 and the value of the mode register 10 are combined by the AND gate 11 when the next event occurs. It is logically ANDed, and is ORed with the address match signal 8 by the OR gate 12, and becomes the address match report signal 13. As a result, it is possible to report the address match even if an event occurs after the number of times is specified.

[0015]

As described above, according to the present invention, the counting circuit for counting the comparison signal output when the main memory address or the micro address and the comparison address match, and the number designation register for designating the number of generations of the comparison signal. The target event occurrence can be easily detected by providing the address match signal when the count number of the comparison signal in the count circuit matches the value of the number designation register.

Further, by providing a flip-flop set when the count circuit and the number-of-times designating register match, and a mode register capable of designating whether or not the comparison signal is logically ORed with the address matching signal, a target event occurrence occurs. The subsequent address coincidence can be easily reported.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 address register 2 comparison address register 3 comparison circuit 4 comparison signal 5 count circuit 6 number designation register 7 address match signal generation circuit 8 address match signal 9 flip-flop 10 mode register 11 AND gate 12 OR gate 13 address match report signal

Claims (2)

[Claims] 1. An address register for storing a main memory address or a microprogram address, and an address for comparing the main memory address or the microprogram address in an address coincidence detection circuit, which is one of means for evaluating or fault analysis of an information processing device. A comparison address register that stores the comparison signal, a comparison circuit that outputs a comparison signal when the results of the comparison match, a count circuit that counts the comparison signal, a number designation register that designates the number of times the comparison signal is generated, An address match detection circuit, comprising: an address match signal generation circuit that generates an address match signal when the output of the count circuit and the value of the number-of-times designating register match. 2. The address coincidence signal generation circuit operates so as to generate an address coincidence signal and set a flip-flop when the output of the count circuit and the value of the number-of-times designating register coincide with each other, 2. A mode register capable of designating whether or not the comparison signal generated after setting a flip-flop is logically ORed with an address coincidence signal is provided.
Address match detection circuit described.