JPS60126740A - Prevention device of cpu runaway - Google Patents

Abstract

PURPOSE:To discriminate CPU runaway securely and to stop a CPU by checking whether or not the prescribed address is accessed and the prescribed data are outputted and discriminate the CPU runaway. CONSTITUTION:When a CPU1 runs away, writing of the prescribed data against the prescribed address will not be executed; therefore an output VN3 of an NOR gate N2, which inputs an output of an access detecting means 2 and that of a data detecting means 3, remains in H level. As a result, a monostable multivibrator M is not triggered, and a capacitor C2 does not discharge. Consequently, after the prescribed period has expired, an input of an invertor I8 exceeds a threshold level voltage, and an output of the invertor I8 becomes ''L'' level. Then a reset signal VR of the CPU1 is outputted, and the CPU1 is reset, thereby stopping runaway. By this device, even if the specific address is accessed, this is considered to be runaway of the CPU1 without a writing operation of the specific data, and therefore CPU1 runaway can be sucurely discriminate.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a CPU runaway prevention device.

[Background technology]

Conventionally, this type of CPU runaway prevention device detects whether a predetermined address set in the program is accessed by the CPU within a certain period of time, and detects that the CPU is running out of control if it is not accessed. I decided that it was a problem and reset the CPU. However, in such a conventional example, even if the CPU goes out of control and executes an instruction that is not on the OJ program, the predetermined address may be accessed; For example, even if the CPU runs out of control, it cannot be determined that the runaway is occurring, and the runaway cannot be stopped. Further, when a loop including an access instruction at a predetermined address is causing a runaway, there is a problem in that the runaway cannot be determined and the runaway cannot be stopped.

[Purpose of the invention]

The present invention has been made in view of the above points, and it is an object of the present invention to provide a CPU runaway prevention device that can reliably determine and stop CPU runaway.

[Disclosure of the invention]

(Embodiment 1) FIG. 1 shows an embodiment of the present invention, in which (1) is a CPU
Then, an instruction is set on the Oj RAM to access a predetermined address and write predetermined data at fixed time intervals T1. (2) is an access detection means such as inverters (11) to (I4) and a Nant gate (N,), and a predetermined address set on the program is detected by the CPU.
It is detected whether or not it is accessed from ill, and a predetermined address (in the first embodiment, 8 pieces of data As = Ats
) is output, an access detection signal vDl is output. (3) is a data detection means consisting of inverters (T5) to (I, ) and NAND game 1/(N2), and predetermined data set on the program (in Example 1, 8-pit data Do to Dy). is output from the CPU +i+, and outputs a data detection signal JpjvD2 when predetermined data is obtained. (4) is a NOR gate (N3), a monostable multivibrator capable of tripping and reset operation, a time constant circuit of υ including a resistor (R1) and a capacitor (C1), and a capacitor (C
2) and a resistor (Rz) (Rs), and an inverter (Is) having a threshold voltage vth. When the detection signals vD1 and VD2 cannot be obtained from T31 at the same time, a reset signal "jVR" is generated for the CPU fl, and the CPU fl is reset.
Stop the CPU U ftl from running out of control. In addition, Example 1
, it is also checked whether the data write signal WR is obtained simultaneously with the detection signals JjjvD1 and V+g. However, the predetermined period T2 is set to be slightly larger than the fixed time T1.

The operation of the first embodiment will be explained below. Now, the CPU
tl) is operating normally, writing of predetermined data to a predetermined address set on the program is performed every fixed time T1, and the detection signal VplsVo2
and the data write signal WR is 〃Ll every time T1.
The output VN3 of the NOR gate (N3) reaches the ILI level at regular intervals Tl as shown in FIG. 2(a). When this output vN3 reaches the trl, t level, the monostable multivibrator is triggered and outputs a pulse with a pulse width determined by the capacitor (C1) and resistor (R1) from the output terminal Q. do. At this time, the electric charge of the capacitor (C2) is discharged via the resistor (R2) every foot time Tl, and the human power v'X of the inverter (I,)
s is the threshold voltage v as shown in the three parts of FIG. 2(b)
th is not exceeded, the inverter output (Is) remains at HI level, the reset signal VR is not output, and the CPU 11) is not reset.

In the unlikely event that CPUflll goes out of control, writing of specified data to a specified address will no longer be possible.
The NOR gate (N3) output VN:S remains at the IHI level, the monostable multivibrator is not tripped, and the capacitor (C2) is not discharged. Therefore, after the predetermined period T has elapsed, the inverter (T8)
When the human power V'x8 exceeds the threshold value ``magnetic pressure vth'', the inverter (T8) output becomes #Ll level and the CPU (11
A reset signal VB is output, the CPU fl) is reset, and runaway is stopped. Here, in the present invention,
Even if a predetermined address is accessed by chance, if there is no write operation for the predetermined data, it will be assumed that the CPU has gone out of control and the CPU will be reset.
tJfl) runaway can be reliably separated, and runaways will not be overlooked as in the conventional example.

(Embodiment 2) FIG. 3 shows another embodiment, in which access detection means (11) to (29) and data detection means detect whether predetermined data has been written to each of a plurality of predetermined addresses. (31) to (3n) are provided to detect whether or not the above writing is performed in a predetermined order within a predetermined period T2, and
Reset means (
4a), and the reset means (4a) is composed of NOR gates (N21) to (Ngn), a sequence circuit, a monostable multivibrator (manufactured) and an inverter (T8) similar to the first embodiment. The sequence circuit (S) consists of NOR gates (N13) to (N2n).
When the output reaches L# level in a predetermined order, it outputs a pulse that triggers a monostable multivibrator.

Currently, a rotaram is installed in the "jO program of the CPU fl) that writes predetermined data to each of a plurality of stored addresses within a certain period of time T1, and if the CPU fl+ is operating normally, the - short Since a write operation of predetermined data to a predetermined address is performed in a predetermined sequence every time T1, the monostable multibyte generator (b) is automatically triggered, and the capacitor t (C2) is discharged.
No reset pulse Vn is generated. On the other hand, CPUfl
) goes out of control, the writing operation of the holdings will not be performed in the above sequence of holdings, and the sequence circuit (
S) Since the output does not reach the L level and the monostable multipipulator is not tripped, the capacitor (C) is not discharged and the input VI8 of the inverter (■8)
When the voltage exceeds the threshold voltage Vth, the reset signal vR
is output, CPUfl+ is reset, and the runaway can be stopped. In this case, since it is checked whether data writing is performed in a predetermined sequence, runaway can be determined more reliably.

Fig. 4 shows another runaway prevention device, in which a pulse width verification circuit (6) is provided to detect the -Hl level period of the output of the I10 port (5), and the I10 The output of port (5) is set to Hl level and IIL level at the end of the main loop, and the pulse width test circuit (6
).

Now, if the CPU (11) is working normally, the I10
A pulse with the specified pulse width (the time width from the start to the end of the main routine) is output from the port (5), and a trigger pulse for the monostable multivibrator (Incorporated) is output from the pulse width detection circuit (6). Ru. Therefore, the capacitor (C2) is discharged at the output of the monostable multivibrator (b), the reset signal vR is not generated, and CPIJf
l) is not reset. On the other hand, if the CPU1l) is running out of control, the pulse width output from the I10 port t-fIsl is no longer the predetermined pulse width, so the pulse width verification circuit (6) sends a tri-force pulse to the monostable multivibrator (b). is not output. Therefore, condensation + j (
ct) is not discharged and the inverter (I
8) exceeds the threshold voltage vth, the reset signal VR is output, the CPU il+ is reset, and the runaway is stopped.

〔Effect of the invention〕

As mentioned above, the invention is to: - set an instruction on the CPU frame to access a predetermined address and write predetermined data every time, and detect whether or not the stored address is accessed by the CPU; Consisting of an access detection means, a data detection means for detecting whether the stored data is output from the CPU, and a reset means for generating a CPU reset signal when the rain detection means output cannot be obtained at the same time within the storage period. Compared to the conventional method, which only checked accesses, it checks whether the stored address is accessed and at the same time checks whether predetermined data is output to determine if the CPU is running out of control. Te CP
This has the effect of being able to more reliably determine if the U is running out of control and bring it to a stop.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram of the same operation as above, FIG. 6 is a circuit diagram of another embodiment, and FIG. 4 is a circuit diagram of another runaway prevention device. +11 is a CPU, +21 (2,) to (2n) are access detection means, +31 (31) to (3n) are data detection means, and tel (4a) is a reset means. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

[Claims] access detection means for setting an instruction to access a predetermined address and writing predetermined data on a CPU controller at fixed time intervals, and detecting whether or not the predetermined address is accessed from the CPU; A data detection means for detecting whether the data is output from the CPU, and a data detection means for detecting whether the data is output from the CPU and the CPU when the output from the rain detection means cannot be obtained at the same time within a predetermined period.
A reset means for generating a reset signal and a different CP
U runaway prevention device.