JPS5690498A - Packaged memory detection system for computer - Google Patents

Packaged memory detection system for computer

Info

Publication number
JPS5690498A
JPS5690498A JP16480779A JP16480779A JPS5690498A JP S5690498 A JPS5690498 A JP S5690498A JP 16480779 A JP16480779 A JP 16480779A JP 16480779 A JP16480779 A JP 16480779A JP S5690498 A JPS5690498 A JP S5690498A
Authority
JP
Japan
Prior art keywords
packaged
memory
hardware
program
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16480779A
Other languages
Japanese (ja)
Inventor
Yutaka Shiihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Facom Corp
Original Assignee
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Facom Corp filed Critical Fuji Facom Corp
Priority to JP16480779A priority Critical patent/JPS5690498A/en
Publication of JPS5690498A publication Critical patent/JPS5690498A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To rapidly and easily detect a packaged memory address of a main memory by adding a simple program using an existing hardware interruption function to a normal program.
CONSTITUTION: The vacant memory address (packaged memory address) spaces that can be used at the current time in a main memory MEM are the packaged memory regions M1, M2 and M3 shown by shaded parts. A program detecting the packaged address spaces in the main memory is executed by making use of a register for hardware abnormal intterruption which is an additional device essential for ordinary hardware, as initial processing of an information processing program. Namely, hardware abnormal interruption is deliberately generated by performing masking of all levels. In this case, it is confined only to the processing process in a register for hardware abnormal interruption, and after the packaged memory addresses are detected and are stored in the predetermined memory regions, the above- mentioned register is reset to a normal state.
COPYRIGHT: (C)1981,JPO&Japio
JP16480779A 1979-12-20 1979-12-20 Packaged memory detection system for computer Pending JPS5690498A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16480779A JPS5690498A (en) 1979-12-20 1979-12-20 Packaged memory detection system for computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16480779A JPS5690498A (en) 1979-12-20 1979-12-20 Packaged memory detection system for computer

Publications (1)

Publication Number Publication Date
JPS5690498A true JPS5690498A (en) 1981-07-22

Family

ID=15800285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16480779A Pending JPS5690498A (en) 1979-12-20 1979-12-20 Packaged memory detection system for computer

Country Status (1)

Country Link
JP (1) JPS5690498A (en)

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