JPH03119437A - Information processor - Google Patents

Abstract

PURPOSE:To detect the design errors by providing an instruction word test circuit which specifies an instruction, a clock number counter which designates the frequency, and another clock number counter which designates the number of clocks counted up to the stoppage of the counter in addition to an instruction address test circuit. CONSTITUTION:An instruction test circuit 51 tests the coincidence between an instruction word register 1 and an instruction word check register 2 in terms of bit '0' held by an instruction word mask register 3. An instruction address test circuit 52 checks whether the instruction address held by an instruction address register 8 is included in a debug section or not. An AND gate 20 secures an AND of outputs between the circuit 51 and the circuit 52, and '1' is given to a frequency counter 21 via a differentiation circuit when the outputs of both circuits 51 and 52 are equal to '1'. Thus the counter 21 subtracts the count value by '1'. When this count value is equal to '0', the output of an AND gate 25 is equal to '1' and a clock stop instruction is produced. Thus the design errors can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device that stops a clock for debugging.

[Conventional technology]

Conventionally, in this type of information processing device, in order to identify the exact part of the error in the design during inspection immediately after design, the clock is stopped when the instruction address is included in a predetermined debug address area, and the clock is stopped at that time. A design error was discovered based on the condition of the equipment.

[Problem to be solved by the invention]

In the conventional information processing device described above, since it is only possible to specify the instruction address, if the instruction at a certain address is executed several times and then an error occurs, the clock is restarted each time the clock stops. Start the
If the operation is required many times until the problem appears, or if an instruction at a certain address takes multiple clocks to execute, the clock will stop immediately after the instruction is released, and the clock will stop until the problem occurs. It is extremely difficult to deal with errors such as when it is necessary to advance several clocks further, or when an instruction word at the same address is rewritten many times by paging, and an abnormality appears only with a specific instruction word among them. The drawback is that it is difficult.

[Means to solve the problem]

The present invention includes an instruction word check register that corresponds to some or all of the bits of the instruction word register, and an instruction word mask register that has the same number of bits as the instruction word check register and also corresponds to the instruction word register. , an instruction word test circuit that tests whether the instruction held in the instruction word register is an instruction specified by the instruction word check register and the instruction word mask register; an instruction debug start address register; an end address register, and tests whether an address held by the instruction address register is included in an instruction debug interval indicated by the instruction debug start address register and the instruction debug end address register. the instruction word test circuit; a number counter that performs a counting operation based on the output of the instruction address test circuit; and a clock number counter that starts counting operation based on the output of the number counter; Configured by instructing to stop the clock.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a clock stop instruction section of an information processing apparatus according to a first embodiment of the present invention.

In FIG. 1, 1 is an instruction word register, 4 is an instruction word length decoder that outputs the instruction word length of the instruction held in the instruction word register, and register 7 holds the instruction word output from the instruction word length decoder. do.

The instruction address register 8 is controlled to set the address of the instruction one machine cycle after the instruction word is set in the instruction word register 1, and the address adder 11
always calculates the address of the next instruction by adding the outputs of the instruction word length register 7 and the instruction address register 8. 2.
3 are an instruction word check register and an instruction word mask register, respectively, and a logic circuit 5 performs an exclusive OR operation (EXNOR) between corresponding bits of the output of the instruction word register 1 and the output of the instruction word check register 2. The logic circuit 6 calculates the logical sum (OR) of the corresponding bits of the output of the logic circuit 5 and the output of the instruction word mask register 3.
) and further logical product (AND) of all those bits.
9 is a flip-flop that receives the output of the logic circuit 6.

14 and 15 are the instruction debug start address 1 register and the instruction debug end address register 1 to 1, respectively;
]-6 is a comparator that detects whether the output of the instruction address register 8 is greater than or equal to the output of the instruction debug start address register 14, and 17 is a comparator that detects whether the output of the instruction address register 14 is the output of the instruction debug end address register 15. This is a comparator that detects whether the output is less than or equal to. 18, 1.9 are AND gates and OR gates, 13 is an instruction address invalid flag, 20, 22.25 are AND gates, and 23 is a clock stop permission flag.

The flip-flop 126 and the AND gate 27 are differentiating circuits that output °°1 only in the first cycle when the output of the AND gate 20 becomes '1'. The AND gate 22 is a counter that increments the count value held by -1'' every time the held count value is '0'', and the AND gate 22 outputs rr 1 ++. 24 is a clock number counter that decreases the count value held by 1'' every machine cycle when the output of the AND gate 22 reaches 1°;
When the held count value is "0", "1" is output to the AND gate 25.

The instruction word test circuit 51 is a circuit that tests whether the instruction word register 1 and the instruction word check register match the bit held in the instruction word mask register 3 which is "'O", and if a match is detected, flip flop 9
PA1'' is set in . Therefore, if all bits of the instruction word mask register 3 are set to 1'', the flip-flop 9 will always be 1'', and the instruction word test can also be invalidated.

The instruction address test circuit 52 tests whether or not the instruction address held in the instruction address register 8 is included in the debug area, and when it is included, outputs one OR gate.
Make it 1''. Instruction address test invalid flag 13 is '
When it is 1'', the output of one OR gate is always 1'', which can invalidate the instruction address test.

The output of the instruction word test circuit 51 and the output of the instruction address test circuit are ANDed by the AND gate 20, and when the outputs of both test circuits are "1", the output is passed through the differentiation circuit made up of the flip-flop 26 and the AND gate 27, and the number of times is counted by the number counter. 21 and AND gate 22 are given '1''. The number counter 21 thereby changes the count value.
``-1''''.If the count value had already become ``0'', the number counter 21 would have outputted 1'', so if the output of the AND gate 20 became a 1 ++, the AND gate would The output of 22 also becomes "1".

This causes the clock number counter to decrease the count value by 1.
'” starts to be performed every clock.The count value is ′
When the clock signal becomes 0'', the output of the AND gate 25 becomes 1, and a clock stop instruction is output.

If the clock number counter is "0" in advance and the AND gate 22 becomes "1", a clock stop instruction is immediately output. Similarly, if the number counter 21 is set to "o" in advance, the number counter will be invalidated, and as soon as the output of the AND gate 20 becomes 1'', the output of the AND gate 22 will become "1". Clock stop permission If the flag 23 is set to "0" in advance, the clock stop instruction will always be '0'°.

FIG. 2 is a block diagram of a clock stop instruction section of an information processing apparatus according to a second embodiment of the present invention.

In FIG. 2, the instruction word test circuit 51. Instruction address test circuit 521 number of times counter 21. Since the clock number counter 24 and the like are exactly the same as those in the information processing apparatus shown in FIG. 1, their explanation will be omitted.

In FIG. 2, instruction decoder 29. Register 30・3
1. The address of the operand is calculated by the address adder 32 and set in the operand address register 33.

The operand address test circuit 53 is configured similarly to the instruction address test circuit 52, and the operand address held in the operand address register 33 is stored in the debug area indicated by the operand debug start address register 35 and the operand debug end address register 36. The comparators 37 and 38 test whether or not it is entered, and the result is outputted by the ant game 10-to 39. If the operand address test invalid flag 34 is not "1'', the output of the OR gate 40 is supplied to the AND gate 28. As a result, the outputs of the instruction word test circuit, instruction address test circuit, and operand address test circuit become "1'' at the same time. ′
’, the number counter 21 passes through the differentiation circuit.
and the clock number counter 24 are driven, and when both counters reach "0", the clock stop permission flag 23 becomes "
If it is 1'', a clock stop instruction is output.

〔Effect of the invention〕

As explained above, the present invention includes, in addition to the instruction address test circuit, an instruction word test circuit for specifying an instruction, a clock number counter for specifying the number of times, and a clock number counter for specifying the number of clocks until stopping. By providing this, it is possible to only stop the clock after a specified clock when a specified instruction word in a specified address range is executed a specified number of times, and this has the effect that design errors can be easily discovered.

Furthermore, if we add an operand address test circuit,
In addition to the above conditions, it is now possible to add a condition such as when an address in a specified range is generated as an operand address, making it possible to issue very detailed lock stop instructions, which is highly effective in discovering design errors. There is also.

[Brief explanation of drawings]

1 and 2 are the first and second embodiments of the present invention, respectively.
FIG. 2 is a block diagram of a clock stop instruction unit in the embodiment. 1... Instruction word register, 2... Instruction word check register, 3... Instruction word mask register, 4... Instruction word length decoder, 5, 6... Logic circuit, 7... Instruction word Length register, 8...Instruction address register, 9.26.
...Flip-flop, 11...Address adder 1
3... Instruction address test invalid flag, 14... Instruction debug start address register, 15... Instruction debug end address register, 16, 17, 37, 38...
Comparator, 18・20・22・25・27・28・
39...AND gate, 19.40...OR gate, 21...Number of times counter, 23...Clock stop permission flag, 24...Clock number counter, 29...
Instruction decoder, 30/31... register, 33...
Operand address register, 34... Operand address test invalid flag, 35... Operand debug start address register, 36... Operand debug end address register, 51... Instruction word test circuit, 5
2... Instruction address test circuit, 53... Operand address test circuit.

Claims (1)

[Claims] 1. An instruction word check register corresponding to some or all bits of the instruction word register, and an instruction word mask having the same number of bits as the instruction word check register and corresponding to the instruction word register in the same way. an instruction word test circuit that tests whether an instruction held in the instruction word register is an instruction specified by the instruction word check register and the instruction word mask register; an instruction debug start address register; an instruction debug end address register, and an instruction address for testing whether an address held by the instruction address register is included in an instruction debug area indicated by the instruction debug start address register and the instruction debug end address register; a test circuit; the instruction word test circuit; a number counter that performs a counting operation based on the output of the instruction address test circuit; and a clock number counter that starts counting operation based on the output of the number counter; An information processing device characterized in that an information processing device instructs to stop a clock by an output. 2. It includes an operand debug start address register and an operand debug end address register, and the address held by the operand address register is included in the operand debug interval indicated by the operand debug start address register and the operand debug end address register. an operand address test circuit for testing whether or not the instruction word test circuit, the instruction address test circuit, and the operand address test circuit perform a counting operation based on the outputs of the instruction word test circuit, the instruction address test circuit, and the operand address test circuit; Equipped with a counter for the number of clocks to start,
2. The information processing apparatus according to claim 1, wherein the clock is instructed to be stopped by an output of the clock number counter.