JPS6111853A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6111853A
JPS6111853A JP59131710A JP13171084A JPS6111853A JP S6111853 A JPS6111853 A JP S6111853A JP 59131710 A JP59131710 A JP 59131710A JP 13171084 A JP13171084 A JP 13171084A JP S6111853 A JPS6111853 A JP S6111853A
Authority
JP
Japan
Prior art keywords
data
program
register
test
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59131710A
Other languages
Japanese (ja)
Inventor
Takeshi Shinoki
剛 篠木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59131710A priority Critical patent/JPS6111853A/en
Publication of JPS6111853A publication Critical patent/JPS6111853A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To test the propriety of the contents of data without reducing the efficiency of data processing by operating a testing means in parallel with the execution of a program. CONSTITUTION:An information processor 2 executes the program, reads out data to be processed from a main storage device 1 and receives the read-out data to a register 3. The data in the register 3 are transferred to the body part 10 of the processor 2 to execute processing such as the calculation of the data and also inputted to the testing means 4. The testing means 4 stores the data in a register 5, compares the contents of the register 5 with a matching pattern read cut from a matching pattern memory 6 by a comparator 7, and if there is no coincidence as the result of comparison with all the matching patterns in the memory 6, ends the test. If the coincidence is detected in the comparator 7, the means 4 stops the test at the time of detection and requests an interruption to the body part 10 of the processor 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、処理データの内容の妥当性を検査する独立の
機構を持つ情報処理装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing apparatus having an independent mechanism for checking the validity of the contents of processed data.

情報処理装置の処理の信頼性を維持する為に、被処理デ
ータの妥当性の検査が行われる。
In order to maintain the reliability of processing by an information processing device, the validity of processed data is checked.

一般に、パリティ検査に代表されるような、データの形
式的検査については、情報処理装置内の諸要所に、いわ
ゆるハードウェア構成の検査回路が設けられ、プログラ
ムによる該データの本来の処理と並行して検査が実行さ
れるように構成されている。
Generally, for formal data checks, such as parity checks, so-called hardware-configured test circuits are installed at various points within an information processing device, and these circuits are installed in parallel with the original processing of the data by a program. The test is configured to be performed by

本発明は、例えばデータの内容が情報処理装置の扱う数
値範囲にあるか等の、データの内容的妥当性検査を行う
手段に関する。
The present invention relates to means for checking the validity of data, such as checking whether the data falls within a numerical range handled by an information processing device.

〔従来の技術と発明が解決しようとする問題点〕従来の
情報処理装置においては、データの内容的妥当性検査を
直接実施するハードウェア機構が無く、検査はプログラ
ムに任されているので、そのような検査を必要とする場
合には、データ処理プログラム中に、検査の為のプログ
ラムを挿入する必要があった・ そのために、単なる検査の為に処理時間を費やし、本来
の目的の処理からみれば処理効率を低下させる結果とな
っていた。
[Problems to be solved by the prior art and the invention] In conventional information processing devices, there is no hardware mechanism that directly performs content validity checks on data, and the checks are left to the program. When such an inspection was required, it was necessary to insert a program for the inspection into the data processing program. This meant that processing time was wasted just for the inspection, and it took away from the original purpose of processing. This resulted in a decrease in processing efficiency.

又、検査プログラムを挿入することが望ましい個所を見
逃した場合には、そのプログラムを実行して、不肖な内
容のデータに遭遇した場合に、プログラマが予測しなか
ったような処理結果を生じることがあめ、そのような予
測しない現象の原因究明は一般に比較的困難であるので
、該データ処理の効率を甚だしく低下させる結果になる
ことがあった。
In addition, if you miss a point where it is desirable to insert an inspection program, if you run that program and encounter data with inappropriate content, processing results that the programmer did not predict may occur. Unfortunately, it is generally relatively difficult to investigate the cause of such unexpected phenomena, which may result in a significant decrease in the efficiency of data processing.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は前記の問題点を解決するための手段として、プ
ログラムを実行してデータを処理するために、主記憶装
置から該データを読み出す場合において、1以上の照合
パターンを保持し、該データの内容が、該照合パターン
の少なくとも1個と一致したときは割込み信号を発生す
る検査手段を有し、上記プログラムの実行と並行して該
検査手段が動作するように構成された情報処理装置・を
提供する。
As a means for solving the above-mentioned problems, the present invention maintains one or more collation patterns when reading data from a main memory in order to execute a program and process the data. An information processing device comprising a checking means for generating an interrupt signal when the content matches at least one of the matching patterns, and configured such that the checking means operates in parallel with execution of the program. provide.

〔作用〕[Effect]

即ち、例えばハードウェアで構成された検査機構を設け
、この検査機構は不当な内容に該当する1以上の照合パ
ターンを記憶して、処理のために主記憶装置から読み出
したデータと照合し、一致した場合には割込み信号を発
生する。
That is, for example, an inspection mechanism configured with hardware is provided, and this inspection mechanism stores one or more matching patterns that correspond to invalid content, matches it with data read from the main storage device for processing, and detects a match. In this case, an interrupt signal is generated.

一般に行われているように、割込み信号は情報処理装置
で実行さているプログラムを中断させて、他の所定のプ
ログラムの実行を強制的に開始させる信号であり、該プ
ログラムにより適当なエラー処理等が可能である。
As is generally done, an interrupt signal is a signal that interrupts a program being executed on an information processing device and forcibly starts execution of another predetermined program, and the program performs appropriate error handling, etc. It is possible.

上記の検査機構による検査動作は、データ処理プログラ
ムの実行を妨げるこ、と無く、プログラムの実行と独立
に並行動作するように構成されるので、検査のためにデ
ータ処理の効率を低下させることは無い。
The inspection operation by the above-mentioned inspection mechanism does not interfere with the execution of the data processing program and is configured to operate independently and in parallel with the execution of the program, so the efficiency of data processing will not be reduced due to inspection. None.

更に、このような検査機構がある場合には、照合パター
ンの1つを予め主記憶装置の所要記憶領域の各語に記憶
させておくことにより、その後該領域のデータを処理す
る場合に、処理している領域部分は有効なデータを入力
済か否かを自動的に検査する等に利用することができる
Furthermore, if there is such a checking mechanism, one of the matching patterns can be stored in advance in each word in the required storage area of the main storage device, so that when data in the area is subsequently processed, the processing This area can be used to automatically check whether valid data has been entered.

〔実施例〕〔Example〕

図は本発明の一実施例を示す。 The figure shows an embodiment of the invention.

主記憶装21はデータ等を記憶する。情報処理装置2は
公知の方法でプログラムを実行し、処理の対象となるデ
ータを主記憶装置1から読み出すと、レジスタ3に受信
する。
The main memory 21 stores data and the like. The information processing device 2 executes a program using a known method, reads data to be processed from the main storage device 1, and receives the data in the register 3.

レジスタ3のデータは、情報処理装置2の本体部10に
転送されて公知の方式で演算等の処理が行われると共に
、検査機構4に入力される。
The data in the register 3 is transferred to the main body 10 of the information processing device 2, where it is subjected to processing such as arithmetic operations using a known method, and is also input to the inspection mechanism 4.

検査機構4はレジスタ5にデータを保持し、レジスタ5
の内容と照合パターンメモリ6から読み出す照合パター
ンとを比較回路7で比較し、不一致であれば次の照合パ
ターンを照合パターンメモリ6から読み出して比較回路
7に入力する。このようにして照合パターンメモリ6の
全照合パターンと比較をした結果、一致が無い場合は検
査を終わる。
The inspection mechanism 4 holds data in the register 5, and
A comparison circuit 7 compares the contents of the comparison pattern with a verification pattern read from the verification pattern memory 6, and if they do not match, the next verification pattern is read from the verification pattern memory 6 and input to the comparison circuit 7. As a result of comparison with all the matching patterns in the matching pattern memory 6 in this way, if there is no match, the test ends.

比較回路7の比較で一致があると、その時点で検査を停
止し、一致信号を割込み信号8として出力することによ
り、情報処理装置2の本体部10に割込みを要求する。
If there is a match in the comparison by the comparator circuit 7, the test is stopped at that point, and a match signal is output as an interrupt signal 8, thereby requesting an interrupt from the main unit 10 of the information processing device 2.

割込みにより本体部10ではエラー処理プログラムが起
動し、処理中のデータの後始末及びエラー原因究明のた
めの状況データの収集等を行うようにすることができる
An error processing program is activated in the main unit 10 by the interrupt, and it is possible to clean up the data being processed and collect status data for investigating the cause of the error.

照合パターンメモリは、例えば読出し専用記憶装置で構
成され、1又は複数の照合パターンを記憶する。1つの
照合パターンはレジスタ3に読みだされるデータと同じ
か又はそれより少ないビット数で構成され、例えば一般
に整数として使用されない°10000・・・−000
”等が検査すべきパターンとなる。
The verification pattern memory is composed of, for example, a read-only storage device, and stores one or more verification patterns. One matching pattern consists of the same number of bits as the data read into register 3 or less, for example, °10000...-000, which is not generally used as an integer.
” etc. are the patterns to be inspected.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように本発明によれば、データ
処理の効率を低下すること無く、データの内容的妥当性
の検査が可能となるので、情報処理装置の性能、信頼性
を改善するという著しい工業的効果がある。
As is clear from the above description, according to the present invention, it is possible to test the content validity of data without reducing data processing efficiency, thereby improving the performance and reliability of information processing equipment. It has significant industrial effects.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例構成のブロック図である。 図において、 1は主記憶装置、   2は情報処理装置、3.5はレ
ジスタ、   4は検査機構、6は照合パターンメモリ
、 7は比較回路、    10は本体部を示す。 代理人 弁理士  検量 宏四部 一30≦
The figure is a block diagram of the configuration of an embodiment of the present invention. In the figure, 1 is a main storage device, 2 is an information processing device, 3.5 is a register, 4 is an inspection mechanism, 6 is a verification pattern memory, 7 is a comparison circuit, and 10 is a main body. Agent Patent Attorney Weighing Koshibe 130≦

Claims (1)

【特許請求の範囲】[Claims] プログラムを実行してデータを処理するために、主記憶
装置から該データを読み出す場合において、1以上の照
合パターンを保持して、該データの内容が、該照合パタ
ーンの少なくとも1個と一致したときは割込み信号を発
生する検査手段を有し、上記プログラムの実行と並行し
て該検査手段が動作するように構成されてなることを特
徴とする情報処理装置。
When reading the data from the main memory in order to execute a program and process the data, one or more matching patterns are retained and the content of the data matches at least one of the matching patterns. An information processing apparatus comprising: a test means for generating an interrupt signal, and the test means is configured to operate in parallel with execution of the program.
JP59131710A 1984-06-26 1984-06-26 Information processor Pending JPS6111853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59131710A JPS6111853A (en) 1984-06-26 1984-06-26 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59131710A JPS6111853A (en) 1984-06-26 1984-06-26 Information processor

Publications (1)

Publication Number Publication Date
JPS6111853A true JPS6111853A (en) 1986-01-20

Family

ID=15064384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59131710A Pending JPS6111853A (en) 1984-06-26 1984-06-26 Information processor

Country Status (1)

Country Link
JP (1) JPS6111853A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6459522A (en) * 1987-08-31 1989-03-07 Nec Corp System for checking data in data processing system
JPH0348939A (en) * 1989-07-17 1991-03-01 Fujitsu Ltd Reference check system for data unset area at program debug
JPH05269070A (en) * 1992-03-25 1993-10-19 Hinode Kk Holder for yarn bundle of mop
JP2008075401A (en) * 2006-09-25 2008-04-03 Jfe Metal Products & Engineering Inc Bracket body for guard fence, and guard fence

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6459522A (en) * 1987-08-31 1989-03-07 Nec Corp System for checking data in data processing system
JPH0348939A (en) * 1989-07-17 1991-03-01 Fujitsu Ltd Reference check system for data unset area at program debug
JPH05269070A (en) * 1992-03-25 1993-10-19 Hinode Kk Holder for yarn bundle of mop
JP2008075401A (en) * 2006-09-25 2008-04-03 Jfe Metal Products & Engineering Inc Bracket body for guard fence, and guard fence

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