JPS6244831A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To speed up processing by stopping the reading and operation of two operands when decimal subtraction is applied and the two operands are superposed. CONSTITUTION:The output of a decimal subtraction instruction detecting part 1 connected to an instruction decode is applied to an OR circuit 4, an address register 2 and an address comparator 3 are connected to an address forming part and the output of the register 2 is applied to the circuit 4 through the comparator 3. The output of the circuit 4 is applied to an FF5 and an OR circuit 6, the output of the FF5 is applied to the circuit 6, the output of the circuit 6 is an operation control part 7 connected to an instruction decode and an address formation control part, and the output of the control part 7 to an operation executing part 8. When the starting address of the 1st operand stored in the register 2 coincides with the starting address of the 2nd operand and a decimal subtraction instruction is applied, address formation and the execution of the operation are stopped by the output from the circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic processing device in an information processing device. In particular, the present invention relates to an arithmetic processing device that performs decimal subtraction at high speed.

〔overview〕

The present invention provides an arithmetic processing device that sequentially reads two operands and performs an operation, and when performing decimal subtraction between two completely overlapping operands, a ``0'' is stored in the memory without performing the operation. It performs subtraction at high speed by outputting.

[Conventional technology]

Conventionally, when performing decimal subtraction in a pipelined arithmetic processing device, two operands are sequentially read out from memory, the operation is executed, and the result is written into memory.

(Problems to be Solved by the Invention) The conventional instruction execution method described above executes an operation even when the two operands to be operated on are the same (complete overlap) and the result is known even if it is not executed. Since the information is stored in memory, the instruction execution time becomes long.

[Means for solving problems]

The arithmetic processing device of the present invention includes a means for reading an operand from a memory, an arithmetic means for performing an arithmetic operation between the two read operands, and an output means for outputting the arithmetic result of the arithmetic means to the memory. The apparatus includes means for detecting that the operation executed by the arithmetic means is a subtraction, means for detecting that two operands completely overlap when the operation is a decimal subtraction, and means for detecting that two operands completely overlap when the operation is a decimal subtraction. The present invention is characterized by comprising means for inhibiting the operations of the reading means, arithmetic means, and output means and outputting "0" to the memory when there is a complete overlap.

[Effect]

When the two operands to be subtracted completely match, the arithmetic processing device of the present invention stops reading and calculating the operands. Therefore, the processing time during this period can be shortened.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

The figure is a block diagram of main parts of an arithmetic processing device according to an embodiment of the present invention.

The input of the decimal subtraction instruction detection unit 1 is connected to the instruction decoder, and the output is connected to the first input of the OR circuit 4.

The input of the address register 2 and the first input of the address comparator 3 are connected to the address generator via a signal line 101. The output of address register 2 is address comparator 3
is connected to the second input of The output of the address comparator 3 is connected to the second input of the OR circuit 4. OR circuit 4
The output of is connected to the flip-flop 5 and the first input of the OR circuit 6. The output of the flip-flop 5 is connected to the second input of the OR circuit 6. The output of the OR circuit 6 is connected to an address generation control section and an arithmetic control section 7. The arithmetic control section 7 is connected to the memory via an instruction decoder, an address generation control section, a control input of the arithmetic execution section 8 , and a selection circuit 9 . The arithmetic execution unit 8 has an input directly connected to the memory and an output connected to the memory via the selection circuit 9.

In the first cycle, the start address of the first operand generated by the address generation section is held in the address register 2 via the signal line 101.

In the second cycle, the start address of the second operand generated by the address generation unit is input to the address comparator 3 via the signal line 101, and the start address of the first operand held in the address register 2 in the first cycle is input to the address comparator 3 via the signal line 101. 3 is similarly input to the address comparator 3. At this time, when address comparator 3 detects a match, its output turns on,
It turns off if no match is detected. Here, this comparison operation is valid only for decimal subtraction instructions, and therefore 10
The output of the base/subtraction instruction detection section 1 and the output of the address comparator 3 are input to the OR circuit 4. The output of the OR circuit 4 is held in a control flip-flop 5.

In the third cycle, the end address of the first operand generated by the address generation section is held in the address register 2 as in the first cycle. In the fourth cycle, the end address of the second operand generated by the address generator is input to the address comparator 3 in the same way as in the second cycle, and in the third cycle, the end address of the first operand held in the address register 2 is also input. It is also input to the address comparator 3.

The match detection result of the address comparator 3 is ORed with the output of the control flip-flop 5 by the OR circuit 6.
It is determined whether or not the operands match in the decimal subtraction instruction. This determination result is reported to the arithmetic control section 7 and the address generation control section.

When this determination result is OFF, the address generation control section instructs the address generation section to calculate a memory address in order to access the storage operand, and performs continuous memory access. On the other hand, when the determination result is 0N (a decimal subtraction instruction and an operand match), the arithmetic control unit 7 notifies the arithmetic execution unit 8 that there is no need to import data or perform an arithmetic operation. Therefore, the output of the calculation execution unit 8 becomes invalid. At the same time, in order to store "0" data, which is the result of the calculation, in the memory, the calculation control section 10 controls the selection circuit 9, and sends the "0" data to the storage address specified by the address generation section.

Note that when the instruction decoder reports to the arithmetic control unit 7 that the instruction is other than a decimal subtraction instruction, the arithmetic control unit 7 ignores the output of the OR circuit 6 and performs arithmetic control. When a decimal subtraction instruction is reported, OR circuit 6
It is recommended to refer to the output of

〔Effect of the invention〕

As explained above, the present invention stores only the known result "0" data without actually reading the operands when the two operands to be operated on match in the decimal subtraction instruction. Finish this command. This has the effect of reducing memory reading, shortening instruction execution time, and improving performance.

The present invention is particularly effective when used in a pipeline type arithmetic processing device.

[Brief explanation of drawings]

The figure is a block diagram of main parts of an arithmetic processing device according to an embodiment of the present invention. 1... Decimal subtraction instruction detection unit, 2... Address register, 3... Address comparator, 4... OR circuit,
5... Control flip-flop, 6... OR circuit,
7... Arithmetic control section, 8... Arithmetic execution section, 9... Selection circuit.

Claims (1)

[Claims] (1) In an arithmetic processing device comprising means for reading an operand from memory, arithmetic means for performing an arithmetic operation between the two read operands, and an output means for outputting the arithmetic result of the arithmetic means to the memory, the above-mentioned operation is performed. means for detecting that the operation performed by the means is subtraction; means for detecting that two operands completely overlap when the operation is decimal subtraction; When the above-mentioned reading means, calculation means and output means are prohibited from operating,
1. An arithmetic processing device comprising: means for outputting "0" to a memory.