JPH03137753A - Access controller - Google Patents

Abstract

PURPOSE:To attain the access of respective internal device in accordance with a decoding condition by deciding access to the arbitrary internal device from the internal device which becomes a common address in accordance with respective internal enable flag and decoding result. CONSTITUTION:A decoder 10 decodes address information of an address bus 15 in accordance with different decoding conditions and outputs decoding output signals 18 and 19 to AND gates 12-14 constituting an address decision means. An enable flag register 11 respectively stores the enable flag for setting registers 26-28 to be the internal devices enabling and outputs enable signals 20-22 to the gates 12-14. Out of chip selection outputs 23-25, the output 23 is outputted to the register 26 by the logical operation of the signal 20 and the signal 18, and the output 25 is outputted to the register 28 by the logical operation of the signal 22 and the signal 18. When the outputs 23-25 are in an 'H' level, a system becomes a selection state and it becomes a direct state when they are in an 'L' level.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an access control device that determines and processes access to internal devices built inside a processor that controls electronic equipment and the like.

[Conventional technology] Conventionally, I of LSI, standard cell, gate array, etc.
When accessing a device inside C, access to each register serving as an internal device was determined by an access control circuit as shown in FIG.

FIG. 3 is a circuit block diagram illustrating an example of a conventional access control circuit, in which 80 is a decoder and an address bus (
An) 81 is decoded, a decode output 83 or a decode output 84 is created depending on its state, and whether or not to access the register 85 or register 86 is determined based on the output state. Note that 82 is a data bus (Dn).

[Problems to be Solved by the Invention] However, in the conventional example described above, since only one I10 device can be accessed for one fil of decoded addresses, there are problems as shown in (1) and (2) below.

(1) Since the decodable area is limited, even if an attempt is made to add a new IO device to the IC, the I10 space may run out.

(2) If there is a malfunction in one part of the IC and you try to replace that function with another IC, it will involve changing the address and it will take a considerable amount of time to change the software.
The burden of system development increases.

This invention was made to solve the above problems, and by providing an enable flag for each internal device to determine whether or not to use each internal device built inside the processor. An object of the present invention is to provide an access control device that can collectively determine accessibility while determining enable flags corresponding to a plurality of different I10 devices allocated to the same address.

[Means for Solving the Problems] An access control device according to the present invention includes a decoder that decodes address information that instructs access to each internal device, and an internal enable that determines access to a plurality of internal devices that have a common address. A flag register that individually stores flags, and a determining means that determines access to any internal device from a plurality of internal devices that serve as a common address according to each internal enable flag stored in this flag register and the decoding result of a decoder. It has been established that

[Effect]

In this invention, when address information instructing access to each internal device is input, the decoder decodes the address information requested for access under various conditions,
The decoding result is output to the determining means. On the other hand, an enable flag indicating whether to enable each internal device is set in the flag register corresponding to each internal device, and based on the enable flag setting state and the address decoding result, multiple It is possible to determine the internal device to be accessed from the internal device.

〔Example〕

FIG. 1 is a block diagram illustrating the configuration of an access control device showing an embodiment of the present invention, in which 10 is a decoder;
The address information on the address bus (An) 15 is decoded according to different decoding conditions, e.g.
Alternatively, the decode output signal 19 is output to AND gates 12 to 14 constituting address determining means.

Reference numeral 11 denotes an enable flag register, which is an enable flag for enabling multiple registers 26 to 28 which are internal devices (instructed by data bus 17).
are individually stored, and enable signals 20-22 are outputted to the AND gates 12-14 as shown.

23 to 25 are chip select outputs, the chip select output 23 is output to the register 26 by a logical operation between the enable signal 20 and the decode output signal 18, and the chip select output 24 is output by a logical operation between the enable signal 21 and the decode output signal 19. The chip select output 25 is output to the register 28 by a logical operation between the enable signal 22 and the decode output signal 18. Note that when the chip select outputs 23 to 25 are at the rH level, the select state is entered, and when the chip select outputs 23 to 25 are at the "L" level, the day select state is entered.

In the access control device configured as described above, when address information instructing access to each internal device is manually inputted to the decoder 10, the decoder 1o decodes the address information requested for access under various conditions and decodes the address information. The results (decode output signal 18 and decode output signal 19) are output to AND gates 12 to 14 constituting the determining means.

On the other hand, in the flag register (enable flag register 11 in this embodiment), an enable flag indicating whether to enable each internal device is set corresponding to each internal device, and this enable flag setting state and address decoding Based on the result, the internal device to be accessed from multiple internal devices having a common address is determined.

Specifically, address bus 15 is decoded by decoder 10, decoded output signal 18 is selected, and r)(
When in the J level state, if the chip select signal 16 of the enable flag register 11 is "H" in advance, the data bit DO of the data bus core is at the rHJ level, and the data bit D2 is at the rLJ level, the enable signal 2 is activated.
0 is rH, level, and enable signal 22 is “L”
Since the logic results of the AND gates 12 and 14 are different, such as "rH" level or "L" level, even when the same common address is selected, the chip select output 23
The register 26 corresponding to the chip select output 25 becomes accessible, but the register 28 corresponding to the chip select output 25 becomes inaccessible.

In this way, even if the decode output signal 19 is selected, the enable output 21 of the enable flag register 11
Depending on the state, the chip select output 24 is set to the selected state or the day select state, and as a result, it is determined whether the register 27 is inaccessible or accessible.

FIG. 2 is a block diagram illustrating the configuration of an access control device showing another embodiment of the present invention, and 40.60 is an IC
Each IC is connected to an address bus 31 and a data bus 32 in parallel.

A decoder 41.61 decodes address information on the address bus 31. 42.62 is an enable flag register, and multiple registers 52.53 are internal devices.
and enable flags (indicated by data bus 17) for enabling registers 72, 73, and enable signals 46, 47 and enable signals for AND gates 48, 49 and AND gates 6B, 69. 66.67 is output as shown.

50.51 is the chip select output, AND gate 48
, 49 to registers 52 and 53 as shown.

70.71 is the chip select output, and gate 68
, 69 to registers 72 and 73 as shown.

Note that the decoding conditions for the decode output signal 44.64 and the decode output signal 45.65 are the same, and the selection conditions for the chip selection 443.63 are also the same.

The operation will be explained below.

If the chip select signal 43 or the chip select signal 63 of the enable flag register 42 or the enable flag register 62 is in the "H" level state in advance, the data bit DO of the data bus 32 is "H", and the data bit D2 is "L" level. , the enable signal 46 is “
When the enable signal 66 is held at the “H” level and the enable signal 66 is held at the “L” level, the address bus 31 is held at the decoder 4
1 or when the decode output signal 44 or the decode output signal 64 is selected by the decoder 61 and is in the "H" level state, the chip select output 50 of the IC 40 is rH,
IC60 chip select output cuff Q
is determined to be r L J level. In this way, even if the same address is selected, the AND gate 48
Alternatively, the output state of the AND gate 62 is different, and the register 52 connected to the chip select output 5o which becomes the AND gate output becomes accessible, but the register 7 connected to the chip select output cuff 0 which becomes the AND gate output.
2 will be restricted from access.

In this way, different internal devices allocated to the same address can be accessed separately even in separate ICs 40 and 60. For example, if a malfunction occurs in a part of the function of the IC, that function can be replaced with another IC. If the need arises, address translation processing is not required and compatibility of the running software can be guaranteed.

〔Effect of the invention〕

As explained above, the present invention includes a decoder that decodes address information instructing access to each internal device;
A flag register that individually stores internal enable flags that determine access to multiple internal devices that serve as a common address, and a flag register that individually stores internal enable flags that determine access to multiple internal devices that serve as a common address, and Since the determining means for determining access from an internal device to an arbitrary internal device is provided, it is possible to arrange a plurality of internal devices having the same address and access each internal device according to decoding conditions. Therefore, it is possible to selectively access a large number of different internal devices in the same address space.

Further, by setting two or more enable flags for internal devices allocated to the same address, excellent effects such as simultaneous writing of data to each corresponding internal device are achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the configuration of an access control device showing one embodiment of the invention, FIG. 2 is a block diagram explaining the structure of an access control device showing another embodiment of the invention, and FIG. FIG. 1 is a circuit block diagram illustrating an example of a conventional access control circuit. In the figure, 10 is a decoder, 11 is an enable flag register, 12 to 14 are AND gates, and 26 to 28 are registers. Figure 1 N2 Figure IC1 No. 40 12~14・AND gate

Claims (1)

[Claims] In an electronic device in which multiple internal devices are connected to the internal data bus of a processor to perform data processing, there is a decoder that decodes address information that instructs access to each internal device, and multiple internal devices that have a common address. A flag register that individually stores internal enable flags that determine access to the internal device, and a common address depending on each internal enable flag stored in this flag register and the decoding result of the decoder. 1. An access control device comprising: determining means for determining access to.