JPS6136652B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic processing device that improves efficiency during testing.

Conventionally, an arithmetic processing device, such as a one-chip microcomputer, has a memory 1 for storing data, an ALU 2 for performing logical and arithmetic operations, and a pair of latches 3 for supplying data to the ALU 2, as shown in FIG. , 4, an accumulator 5 that temporarily stores the arithmetic processing results in the ALU 2 or data read from the memory 1, and an output register (hereinafter referred to as an output port) 6 that temporarily stores data to be supplied to the outside. an internal bus 7 for transferring data between the internal bus 7 and the input gates G _{I1 to} G I5 and the output gates G O1 to G _I5 provided between the internal bus 7 and the memory 1 to the output port ₆ , respectively;
G _O3 and gate control signals SM, DM, DX, DY, SZ, SA, for controlling the opening and closing of each of these gates.
It is composed of a control circuit 8 that outputs DA and DO.

By the way, let us consider the case of testing whether or not the following instructions among the basic instructions of the microcomputer are correctly executed in the above-mentioned conventional microcomputer.

LD A←M ADD A←A+M However, the above instruction LD means a load instruction, and its processing purpose is to transfer the contents of memory 1 to accumulator 5, as shown by the symbol on the right side. ADD means an addition command, and its processing content is to add the contents of the accumulator 5 and the contents of the memory 1 and store the result in the accumulator 5 again.

When the above load command LD is executed, the gate control signals SM and DA from the control circuit 8 become active, and the output gate G _O1 and the input gate G _I4 are activated.
is opened, and data from memory 1 is transferred to accumulator 5 via internal bus 7. addition instruction
When ADD is executed, first the gate control signals SA and DX become active, the output gate G _O3 and the input gate G _I2 are opened, and the data stored in the accumulator 5 is stored in one latch 3. Then gate control signals SM and DY
becomes active, the output gate G _O1 and the input gate _I3 are opened, the data in the memory 1 is stored in the other latch 4, and finally the gate control signal SZ
and DA become active, the output gate G _O2 and the input gate G _I4 are opened, and the addition result in ALD2 is stored in the accumulator 5. However, this order of processing is for convenience, and depending on the number of internal buses 7 and the configurations of ALU 2 and accumulator 5, processing may be performed simultaneously.

When testing the execution of a load instruction or addition instruction as described above, since the accumulator 5, ALU 2, memory 1, etc. are housed inside a single chip IC, it is not possible to test the execution immediately, and the microprocessor with output port 6 is In the case of a computer, it is necessary to execute the following output instruction after the load instruction or addition instruction described above.

OT O←A This instruction is similar to the load instruction described above, and activates the gate control signals SA and DO from the control circuit 8, opens the output gate G _O3 and the input gate G _I5 , and loads the data stored in the accumulator 5. This data is transferred to the output port 6 via the internal bus 7. In other words, the data can only be observed by executing this instruction following the instruction or the instruction.
The load instruction was executed correctly or ALU2
It becomes possible to test whether the addition process was performed correctly. Furthermore, in microcomputers without an output port 6, by executing some instructions that transfer data from the internal bus 7 to the external bus (for example, an instruction to store to external memory or an instruction to transfer to an external input/output device). testing becomes possible.

Furthermore, when testing data by reading it from memory 1, a combination of a load instruction, an output instruction OT, and an instruction for updating the memory address is required for each data in one address of memory 1.
The combination must be repeated for all addresses in memory 1.

As described above, the conventional method has the disadvantage that when performing a test, an extra instruction is required to output data to the outside, making the test sequence long and making it impossible to perform the test efficiently.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to eliminate the need for extra instructions for outputting data to the outside when performing a test. An object of the present invention is to provide an arithmetic processing device that can efficiently perform the following operations.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block configuration diagram when the arithmetic processing device according to the present invention is implemented in a one-chip microcomputer in the same way as in the prior art, and parts corresponding to those in the conventional device shown in FIG. 1 are given the same reference numerals. The explanation will be omitted.

In the device of this embodiment, the gate control signal DO from the control circuit 8 is not directly applied to the input gate _GI5 , but is applied via the OR gate circuit 9, and the test mode signal TEST applied from the outside, Input gate G of accumulator 5
The output of the AND gate circuit 10 which is given in parallel with the gate control signal DA given to _I4 is ORed.
The signal is applied to the input gate G _I5 via the gate circuit 9.

In the device having such a configuration, in the test mode in which the test mode signal TEST is active, the AND gate circuit 10 is opened.
In addition to the normal gate control signal DO, the input gate G _I5 of the output port 6 is also supplied with the same gate control signal DA as that applied to the input gate G _I4 . Therefore, when an instruction that changes the contents of the accumulator 5 is executed in the test mode, the input gate G _I5 of the output port 6 and the accumulator 5 are changed by one gate control signal DA.
Since two of the input gates G _I4 are opened, the transfer results or calculation results transferred on the internal bus 7 are not only stored in the accumulator 5 but also in the output port 6 at the same time. As a result, the results of transfers and calculations can be immediately observed without executing output instructions as in the conventional case, and the test sequence can be shortened.

For example, if you want to read and test the contents of memory 1, you can simply repeat the combination of a load instruction and a memory address update instruction for each memory 1 address (some computers often do not allow loading and updating memory addresses at the same time). In this case, the test sequence can be significantly shortened.

As described above, according to the above embodiment, when performing a test, an extra instruction for outputting data to the outside is not required, so that the test can be performed efficiently.

Note that the present invention is not limited to the above-mentioned embodiments; for example, the case where the output port 6 is provided for outputting data to the outside has been described; however, this is a terminal simply connected to the internal bus 7; It's okay. In addition, we have explained the case where a pair of latches 3 and 4 are provided on the input side of ALU2.
This may be provided on the output side of ALU2, and the accumulator itself may be used instead of the latch.

As explained above, according to the present invention, in the test mode, the input gate means provided on the input side of the output means for generating data to be supplied to the outside, and the input gate means provided on the input side of the accumulator. Since the same signal as the applied gate control signal is applied, it is possible to provide an arithmetic processing device that can perform tests efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional arithmetic processing device, and FIG. 2 is a block diagram of an embodiment of the present invention. 1...Memory, 2...ALU, 3, 4...Latch, 5
...Accumulator, 6...Output register (output port), 7...Internal bus, 8...Control circuit, 9...OR gate circuit, 10...AND gate circuit, G _I1 to G _I
5 ...Input gate, G _O1 to G _O3 ... Output gate.

Claims (1)

[Claims] 1. An internal bus, a control section, an accumulator connected to the internal bus to which data on the internal bus is transferred, and an accumulator provided on the input side of the accumulator and controlled to open and close by a gate control signal from the control section. a first input gate means; an output means connected to the internal bus for generating data to be supplied to the outside; and a gate provided on the input side of the output means and applied to the first input gate means in a test mode. An arithmetic processing device comprising: second input gate means whose opening and closing are controlled by the same signal as the control signal.