JPH04205435A - In-circuit emulator device - Google Patents

Abstract

PURPOSE:To simply and effectively execute circuit emulation by providing this in-circuit emulator device with an in-circuit emulation means and an adaptor circuit for connecting/disconnecting an MPU address bus to/from an MPU/ DRAM address bus based upon a memory control signal. CONSTITUTION:Control signals such as a row address selection signal nRAS and a column address selection signal nCAS are outputted from a DRAM controller 4 to a DRAM block 6. Only when these signals are outputted at the reading or writing timing from/in the block 6, they are detected by a three-state buffer control circuit 11. Thereby a three-state buffer 9 is set up to high impedance by an enable signal EN and the generation of address interference between the MPU address bus 2 and the MPU/DRAM row/column address bus 7 can be prevented. Thus in-circuit simulation can be simply and accurately executed while preventing the generation of address interference.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an in-circuit emulator device, and particularly to a dynamic random access memory (DRAM).
) An in-circuit emulator device suitable for use in implementing in-circuit emulation of a target circuit comprising a controller and a microprocessor.

(Prior Art) FIG. 2 is a block diagram of a microprocessor system including a boat fishing RAM. As shown in FIG. 2, an MPU 7 address bus 2 and a data bus 3 are connected to the microprocessor 1.

The data bus 3 is connected to the DRA M block 6.

Address control for the DRAM block 6 is performed via the DRAM controller 4.

A kfPU address bus 2 and a chip select signal n are connected between the microprocessor 1 and the DRAM controller 4.
It is connected at C5 (-C5). Between the DRAM controller 4 and the DRAM block 6 are a DRAM row/column address busler and a row address selection signal nR.
AS (=RAS) and column address selection signal nCA
S (=CAS) and write enable signal n W E
(-W E ).

In the above configuration, control of the DRAM block 6 from the microprocessor 1 is performed as follows.

That is, from microprocessor 1 to MPU address bus 2
, applies an address to the DRAM block 6 via the DRAM controller 4 and the DRAM row/column address bus 5. This specifies the address of the DRAM block 6. On the other hand, the chip select signal nC3
Select M controller 4. This allows DRA
Row address selection signal nRAS from M controller 4,
Column address selection signal nCAS and write enable signal nWE are output. As a result, D RA Fv1
Controls writing/reading of data to/from block 6. Then, input/output of write/read data is executed through the data/1 bus 3.

In the above configuration, the MPU address bus 2 for the microprocessor 1 and the DRAM row/column address bus 5 for the DRAM block 6 are separate dedicated address lines. Therefore, there is no interference between each address. Therefore, it is possible to easily connect and operate an in-circuit emulator device for emulating the operation of the microprocessor 1.

On the other hand, FIG. 3 is a block diagram illustrating a configuration in which the DRAM controller 4 is built into the microprocessor 1. As shown in FIG. 3, the DRAM controller 4
is built into the microprocessor 1, the microprocessor 1 receives the MPU address bus 2 and the DRAM row/column address bus 5 dedicated to the DRAM block 6.
Further, the DRAM controller 4 built in the microprocessor 1 directly sends a row address selection signal nRAS, a column address selection signal nCAS, and a write enable signal nW to the DRAM block 6.
E is output.

In the above configuration, control of the DRAM block 6 by the microprocessor 1 is performed as follows.

That is, the microprocessor 1 directly accesses the DRAM block 6 via the DRAM row/column address busler.
Specify the address of.

On the other hand, the microprocessor 1 directly outputs the row address selection signal nRAS and the column address selection signal nCASs write enable signal nWE to the DRAM block 6. Thereby, writing/reading of data to/from the DRAM block 6 is controlled.

Further, through the data bus 3, data is written to and read from addresses specified by the DRAM row/column address bus 5.

Even in the above configuration, the MPU address bus 2 for the microprocessor and the DRAM block 6
It is separated from the RAM row/column address bus 5. Therefore, an in-circuit emulator device for emulating the operation of the microprocessor 1 can be easily connected and operated.

(Problem 8 to be Solved by the Invention) However, the devices shown in FIGS. 2 and 3 have a drawback in that the number of address lines increases. That is, as in the configuration shown in FIG.
The DRAM block 6 may be controlled through the AM row/column address bus 5, or another DRAM row/column address bus 5 may be derived from the microprocessor 1 as shown in the configuration shown in FIG. In a configuration in which 6 addresses are specified, it is unavoidable that the number of address lines increases. In particular, considering the future increase in the bit size of the DRAM block 6, the number of address lines will increase, or a significant waste will be caused in terms of circuit configuration.

Considering the above, the inventor came to the following consideration. That is, as shown in the block diagram of FIG. 4, a target circuit block 13 as an emulation target including a microprocessor 1 and a DRAM controller 4
From there, a data bus 3 and an MPU/DRAM row/column address bus 7 are derived and connected to the DRAM block 6. Then, the row address selection signal nR
A possible method is to control the DRAM block 6 using the A S column address selection signal nCAS and the write enable signal nWE. In such a system, when the microprocessor 1 is activated and the internal DRAM operates, it is possible to design the system so that the address of the microprocessor 1 and the address of the DRAM block 6 do not interfere internally.

However, when developing such a microprocessor system, it is necessary to use the IC during debugging work.
Is it necessary to verify the system using E? In this case, the main microprocessor for emulation is not the microprocessor 1 in the target circuit block 13, but the microprocessor in the ICE. In this case, an in-circuit emulator device is required to prevent interference between the address for setting the address of the DRAM block 6 from the target circuit block 13 and the address of the microprocessor in the target circuit block 13.

The present invention has been made in view of the above, and its purpose is to:
The address line for DRAM row/column address setting and the address line from the emulator are shared via an adapter, and the adapter connects and disconnects the two address lines as appropriate to prevent address interference. This prevents the increase in address lines.
An object of the present invention is to provide an in-circuit emulator device that can easily and effectively perform circuit emulation.

[Structure of the invention]

(Means for Solving the Problems) The gist of the present invention is an in-circuit emulator device that performs in-circuit emulation of a target circuit having a microprocessor and a DRAM controller, the target circuit having an MPU/DRAM address bus color address. a DRAM whose addressing and data writing/reading are controlled by a memory control signal; and a DRAM connected to the target circuit via a data bus and a control bus, from which an MPU address bus is derived. an in-circuit emulation means for emulating a target circuit, the MPU address bus and the MPU/DRAM;
and an adapter circuit that disconnects the MPU address bus from the MPU/DRAM address bus based on the memory control signal.

(Function) In the in-circuit emulator device of the present invention,
When accessing the DRAM from the in-circuit emulation means through the target circuit, this access is detected based on a memory control signal output from the target circuit. And with the adapter circuit,
MPU address bus derived from in-circuit emulation means, target circuit means and DRA
The MPU/DRAM address bus connecting the M blocks 6 prevents address interference.

(Example) The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an in-circuit emulator device according to an embodiment of the present invention. In this Figure 1,
An in-circuit emulator (ICE) 10 connects data to a target circuit block 13 as an emulation target and a DRAM block 6 via a data bus 3. Then, between the target circuit block 13 and the DRAM block 6, there is an MPU
/D RAM row/column address bus 7. MPU/DRAM row/column address bus 7
and the MPU address bus 2 for ICEIO are connected via a 3-state buffer 9.

3-state buffer 9 and 3-state buffer control circuit 1
1 constitutes the ICE adapter circuit 12. The three-state buffer control circuit 11 is supplied with a row address selection signal nRAS and a column address selection signal nCAS from the target circuit block 13, and further receives a clock signal CLK and a reset signal nRESET (-RESET) from the outside. Ru. 3-state buffer control circuit 1 to 3-state buffer control circuit 9
An enable signal EN is output.

For the target circuit block 13 to DRA k1 block 6, a row address selection signal nRAS.

Column address selection No. 16 n CA S s write enable signal nWE is given.

The operation of the above configuration will now be described.

First, in order to emulate the ICEI (target circuit block by the microprocessor on the 1 side) 3, the DRAM controller 4 on the target circuit block 13 side is activated.In this case, the DRAM controller 4 sends a row address to the DRAM block 6. Control signals such as a selection signal nRAS and a column address selection signal nCAS are output.These signals are output in three steps only when they are output at the timing for reading or writing to the DRAM block 6. This is detected by the MPU address bus 2. This causes the enable signal EN to set the 3-state buffer 9 to high impedance.
Address interference between the MPU/DRA~1 row/column address bus 7 is prevented. This allows the address generated by the DRAM controller 4 to be input to the DRAM block 6.

Next, if the row address selection signal nRAS or column address selection signal nCAS is not output from the DRAM controller 4 of the target circuit block 13,
A case will be described in which, even if the signal is output, it is not the timing to read or write to the DRAM block 6.

In these cases, the enable signal EN from the 3-state buffer control circuit 11 causes the 3-state buffer 9 to pass through. This allows MPU address bus 2 and MPU address bus 2 to
The PU/DRAM row/column address bus 7 is in a connected state. This allows those buses to
It will be used for purposes other than accessing the AM block 6.

As a result, when DRAM block 6 is accessed, D
Address of RAM row/column address bus 7 and MPU address bus 2 connected to microprocessor 1
addresses and can be prevented.

In addition, in the above embodiment, the MPU address bus 2 and the MPU
A case has been exemplified in which the connection and disconnection with the /DRAM row/column address bus 7 is performed by a 3-state buffer 9. However, an equivalent function can also be provided by electronic switching means.

〔Effect of the invention〕

According to the present invention, when performing in-circuit emulation of a target circuit incorporating a DRAM controller, an adapter is used to connect or disconnect the address bus on the in-circuit emulator side and the address bus on the DRAM side. , it is possible to easily and reliably perform in-circuit emulation while preventing an increase in address lines and address interference.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an in-circuit emulator device according to an embodiment of the present invention, FIG. 2 is a block diagram of a microprocessor system including a general RAM, and FIG. 3 is a block diagram of a microprocessor system including a DRAM. D
FIG. 4 is a block diagram illustrating a configuration including a built-in RAM controller. FIG. 4 is a block diagram of a system in which a microprocessor address bus and a DRAM address bus are shared. 1... Microprocessor, 2... MPU address bus, 3... Data bus, 4... DRAM controller, 5... Row/column address bus for DRAM, 6... DRAM Block, 7...MPU/
DRAM row/column arrow/column address bus troll bus, 9...3 state buffer, 10...
ICE. 11...3 step buffer control circuit, 12...I
CE adapter circuit, 13...Target circuit block. Applicant's agent Mr. Sato Figure 3 (Conventional example)

Claims (1)

[Scope of Claims] An in-circuit emulator device that performs in-circuit emulation of a target circuit having a microprocessor and a DRAM controller, the device being connected to the target circuit through an MPU/DRAM address bus, and capable of specifying addresses using memory control signals. A DRAM in which data writing/reading is controlled; and an in-circuit for emulating the target circuit, which is connected to the target circuit via a data bus and a control bus, and from which an MPU address bus is derived. emulation means, interposed between the MPU address bus and the MPU/DRAM address bus, emulating the MPU based on the memory control signal;
An in-circuit emulator device comprising: an adapter circuit for connecting/disconnecting between a U address bus and an MPU/DRAM address bus.