JPH0359740A - Memory fault detection system - Google Patents

Abstract

PURPOSE:To reduce the cost of the system and to completely check a memory by storing data whose all bits are reset in the same address, reading out the stored data, collating the read data with the original data, and at the time of detecting a memory fault, displaying an error on an error display FF circuit. CONSTITUTION:The system is provided with a timer circuit 9 for generating a periodical interruption signal to a CPU 1 and the error display FF circuit 8 for displaying an error at the time of generating a fault in the memory 3. When an interruption signal arrives, the address of the memory 3 is updated, data whose all bits are reaset are stored in the updated address and then read out and the read data are collated with the original data. When a memory fault is detected as the result of comparison, the error is displayed on the circuit 8. Consequently, complete memory check is attained without increasing the cost.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory fault detection method for detecting a memory fault in a system including a CPU and a memory.

[Prior art] A block diagram illustrating a conventional memory fault detection method is shown in the third section.
As shown in the figure. In the figure, 1 is the CPU, 2 is the CPU bus, 3 is the memory connected to the CPU bus 2, and 4 is the memory 3.
A parity generator 5 generates parity bits from data written in the parity generator 4, a valid bit holding memory 5 holds the parity bits generated in the parity generator 4, and a bit holding memory 6 checks the data read from the memory 3 and the parity bit holding memory 5, respectively. 7 is an error detection circuit that detects errors from the data output from the parity checker 6;
is an error display F/F circuit that displays the error output from the error detection circuit 7.

In the system configured as described above, when detecting a memory fault, the memory fault is detected as follows. That is, when the CPU 1 writes data to the memory 3, this write data is sent to the parity generator 4. Then, the parity generator 4 generates a parity bit from this write data and sends it to the parity bit holding memory 5 to be held there.

Next, when the CPUI reads the data written above to the memory 3, the read data is sent to the parity checker 6, and at the same time, the held parity bit is transferred from the parity bit holding memory 5. The data is read out and sent to the parity checker 6. Then, the parity checker 6 sends the held parity bits of the write data and the parity bits of the read data to the error detection circuit 7. The error detection circuit 7 compares and collates both parity bits, and when an error is detected, sends an error signal to the error display F/F circuit to display an error.

Note that if the data written to the memory 3 and the data read from the memory 3 are compared and the number of failure bits in the read data is an even number, error detection cannot be performed at this time.

[Problem H to be Solved by the Invention] The conventional memory fault detection method described above uses a parity generator 4. Parity bit holding memory5. Additional circuits such as a parity checker 6 and an error detection circuit 7 are required, and as the memory capacity of the memory 3 increases, the capacity of the parity bit holding memory 5 also increases, resulting in an increase in cost. Another problem is that when comparing the data written to the memory 3 and the data read from the memory 3, if an even number of bits in the read data becomes a fault, the error in the faulty bit cannot be detected. There was also.

[Means for Solving the Problems] In order to solve such problems, the memory fault detection method of the present invention includes a timer circuit that generates periodic interrupt signals to the CPU, and an error display when a memory fault occurs. It is equipped with an error display F/F circuit that performs error display.

[Operation] When an interrupt signal arrives, the memory address is updated, and after storing data with all bits set at this address, this data is read and verified, and then all bits are reset at this same address. After storing the data, this data is read out and verified. As a result of this verification, if a memory failure is detected, an error message will be displayed F/
Displays an error on the F circuit.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an example of the memory fault detection method of the present invention. In this figure, the same parts as those in the block diagram of the conventional memory failure method shown in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted. In FIG. 1, 9 is a timer that periodically generates an interrupt signal to the CPUI.

The period of this timer 9 is set to 16 m5. In addition, CPU bus 2 is a 16-bit address bus and
It consists of a 6-bit data bus.

The timer 9 detects a fault in the memory 3 when the CPU
By generating a periodic interrupt signal to I, this is done during the interrupt processing that the CPUI receives and executes, and if an error is detected as a result of this processing, an error display will be displayed on the F/F. Error display information is sent to the circuit 8 to display the error.

Next, FIG. 2 is a flowchart illustrating the operation of this memory fault detection method. The detailed operation of the memory fault detection method will be explained based on this flowchart.

When the CPUI accepts the interrupt signal from timer 9,
When interrupt processing is executed, in step 100 the data in the memory 3 indicated by the address counter inside the CPUI which has been cleared to "O" in advance is read out, and in step 101 the read data is saved in another register inside the CPUI. This data is saved for use in normal processing. Next, in step 102, 16-bit data FFFFH (FFFF in hexadecimal) is stored at the address in memory 3 indicated by the address counter with the same value as above.
Write the data. Then, the data at the same address in the memory 3 into which the command was written in step 103 is read out.

In step 104, this read data (read data)
is write data (write data), i.e. FFFF
Determine whether it matches H. And this is "Y"
In other words, if it matches the written data, then in step 105, 16-bit data 0OOOO is written to the address of memory 3 indicated by the address counter with the same value as above.
Write H (data oooo in hexadecimal). Then, the data at the same address in the memory 3 into which the command was written in step 106 is read out.

In step 107, it is determined whether the read data matches the write data, that is, 0OOOH. If this is "Y", that is, if it matches the written data, the data saved in another register is written to the address of memory 3 indicated by the address counter in step 108, and the address counter is set to 2 in step 109. It counts up the address and returns from interrupt processing. In this way, during this interrupt processing, a fault in memory 3 at addresses 0 and 1 is detected, and in the next interrupt processing after 16IIIs, a fault in memory 3 at addresses 3 and 4 is detected. It will be done.

If the result in step 104 is "N", that is, the read data is not FFFFH, the error display information is set in the error display F/F circuit 8 in step 110, and the process returns from the interrupt processing, and the result in step 107 is "N", that is, when the read data is not FFFFH. If the read data is not 0OOOH, step 11
When the value is 0, error display information is set in the error display F/F circuit 8 and the process returns from the interrupt processing.

As mentioned above, in the case of this embodiment, fault detection in the memory 3 is performed in between normal processing executed by the CPU, that is, during timer interrupt processing other than normal processing, memory faults are detected at two addresses every 16m5. ing. Since the memory 3 is a 64-byte RAM, 32,000 interrupt processes are required to check this data. That is, to detect a fault in all areas of the memory 3, it takes 16w5×32000=512S, that is, 512 seconds.

In addition, since the 16-bit data to be read and written to memory 3 is checked based on two types of data: data FFFFH in which all bits are set and data 0000H in which all bits are reset, all bit combinations of data are checked. can be checked, and a perfect memory check can be performed.

[Effects of the Invention] As explained above, the memory failure method of the present invention includes a timer circuit that generates periodic interrupt signals, and an error display F/F circuit that displays an error when a memory failure occurs.
When an interrupt signal arrives, the memory address is updated, the data with all bits set is stored at this address, this data is read out and compared, and the next data with all bits reset is stored at this same address. After being stored, this data is read out and verified, and if a memory failure is detected as a result of this verification, an error is displayed on the error display F/F circuit, so the additional circuitry involved in memory failure detection can be reduced. In addition to being able to reduce costs, it is also possible to detect faults in all bits of all memories, resulting in the effect that a complete memory check can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the memory failure method of the present invention, FIG. 2 is a flowchart explaining its operation, and FIG. 3 is a block diagram explaining a conventional memory failure method. Engineering...CPU, 2... -CPU bus, 3.
...Memory, 8...Error display 171 circuit, 9.
...Timer.

Claims (1)

[Scope of Claims] A memory fault detection method for detecting a memory fault in a system including a CPU and a memory, comprising: a timer circuit that generates a periodic interrupt signal to the CPU; and an error display when the memory fault occurs. and an error display F/F circuit that stores data with all bits set at the address of the memory that is updated every time the interrupt signal arrives, and then reads and collates the data, and also displays data with all bits set at the address. A memory failure detection method characterized in that reset data is stored and then read out and verified.