JPH02113648A - Error information storing device - Google Patents

Abstract

PURPOSE:To improve fault search and debugging efficiency by transmitting an error detecting signal and a bus slave code by means of a bus slave circuit, and providing a slave card error detecting part, an error information read part and an error information preserving part at a bus master circuit. CONSTITUTION:A slave card error detecting part 8, an error information read part 9 and an error information preserving part 10 are provided at a bus slave circuit 1, and further an error detecting signal line 7 is provided between the bus master circuit 1 and a bus slave circuit 3. Further, when data are transmitted between the bus master circuit 1 and the bus slave circuit 3, and the error is generated in the bus slave circuit 3, the error information is read from the error information storing part of the bus slave circuit 3, and stored into an error information preserving part 10 of the bus master circuit 1. Consequently, the relation between the error generated in the bus master circuit 1 and the error generated in the bus slave circuit 3 can be easily separated. Thus, the fault search and debugging efficiency can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error information storage device, particularly to storage of error information in a multiprocessor type programmable control device.

[Prior Art] A conventional error information storage device is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-6
It was disclosed in Japanese Patent No. 8952, and was as shown in the block diagram shown in FIG. In Figure 6, system bus (2) to which bus master circuits (>1) to (1-N) are connected
Bus slave circuits (3-1) to (3-M) are connected to the bus slave circuits (3-1) to (3-M), and error information generating units (5-1) to (3-M) are connected to the bus slave circuits (3-1) to (3-M). 5-M) and error information storage units (6-1) to (6-M). In addition, the bus master circuits (1-1) to (1-N) include
Bus master code addition circuits (41) to (4-N) are provided.

Next, the operation will be explained. In FIG. 6, when any of the bus master circuits (], -1) to (1-N) accesses any of the bus slave circuits (3-1,) to (3-M), the accessing bus master circuit circuit (e.g. (
1-1)) The path master code addition circuit (1-1) is as follows:
A unique bus master code is attached to the address for access (the address of the bus slave circuit to be accessed and the memory address if the bus slave circuit is a memory, for example) and sent onto the system bus (2). When the bus slave circuit (for example (3-1)) specified by this address receives an access, data is transferred between the bus slave circuit and the access source bus master circuit (1-1). Regarding this data transfer, when an abnormal state such as a parity error is detected in the bus slave circuit (3-1), the bus slave circuit (3-1) is notified of the error by the error information generation circuit (5-1). Create information and store it in the error information storage section (6-1). The error information stored consists of the error content, the address related to the bus slave, and the path master code of the accessing bus master.The error information is read from each bus slave by the bus master circuit that performs logging processing and is stored as error logging. be done.

[Problems to be Solved by the Invention] Conventional error information storage devices are configured as described above, so even if an error occurs in the bus slave circuit due to an error occurring in the bus master circuit, the error is not detected. Information is registered separately in the bus master circuit and bus slave circuit and logged asynchronously with the occurrence of an error, so when analyzing error information, it is necessary to correlate errors that occur in the bus master circuit and errors that occur in the bus slave circuit. Things are difficult.

Therefore, in some cases, it may be necessary to analyze the behavior of the program in the bus master circuit, which poses a problem in that troubleshooting and debugging operations become extremely inefficient.

The present invention has been made to solve such problems, and an object of the present invention is to provide an error information storage device that can clearly determine the mutual relationship of error information between a bus master circuit and a bus slave circuit. shall be.

[Means for Solving the Problems] The error information storage device according to the present invention provides a means for solving the problem when data is transferred between a bus master circuit and a bus slave circuit.
A slave card that recognizes that an error has occurred in the bus slave circuit by accepting the error detection signal and bus slave code sent by the bus slave circuit according to the transmitted bus master code when an error is detected in the bus slave circuit. It has an error detection section, an error information reading section that reads the error information from the error information storage section of the bus slave circuit, and an error information storage section that sequentially stores the read information to clarify the mutual relationship of the error information. It is something.

[Operation] According to the present invention, the bus slave circuit transmits an error detection signal and the bus slave code, and the bus master circuit includes a slave card error detection section, an error information reading section,
By providing an error information storage section, error information that occurs in the bus slave circuit can be stored in the error information storage section of the bus master circuit, and errors that occur in the bus master circuit and errors that occur in the bus slave circuit can be stored. This makes it possible to create a relationship with the program, improving debugging efficiency.

[Example] Next, the present invention will be explained in more detail by way of an example not shown in the drawings.

FIG. 1 shows an embodiment of an error information storage device according to the present invention, in which the same or equivalent parts are given the same reference numerals as the reference numerals in FIG. 6 showing the prior art.

In Figure 1, bus master circuits (1-1) to (1-N
) and the bus slave circuits (3-1) to (3-M) are
While connected to the system bus (2), it is also connected to an error detection signal line (7).

The bus master circuit (1, -1) to (>N) has a second
As shown in the figure, the Bassmaster Tacho-Toy 1 addition circuit (4-1
), a slave card error detection section (8) connected to the error detection signal line (7), and an error information reading section ( 9) and an error information storage section (10) that stores the error information read by the error information reading section (9).

As shown in FIG. 3, the error detection signal supplied from the bus slave circuit to the slave card error detection section via the error detection signal line (7) is a bus slave code (for example, BMOLBMI, 8M2.8M3) and an error detection signal. detection signal (ER). In response to this error detection signal, error information (1>1) (
1, 1-2), (11-3), etc. are stored sequentially as shown in FIG. The details of each error information (for example, 1l-1) are as shown in FIG. A slave code (13) and error information (14) are written. Next, the operation of such an error information storage device will be explained. Since the normal basic operation is the same as that of the prior art, it will be omitted here. For example, when data is transferred to a bus master circuit (1-1) or a bus slave circuit (3-1), if an error occurs in the bus slave circuit (3-1), the bus slave circuit (3-1) uses the bus master code to When a bus master circuit is recognized, an error detection signal as shown in FIG. 3 is returned to the corresponding bus master circuit. The error detection signal is sent to the slave card error detection section (8) of the bus master circuit (11) via the error detection signal line (7).
) is entered. This slave quad error detection section (8)
decodes the error detection signal and, for example, if it determines that this error detection signal is from the bus slave circuit (3-1), the slave card error detection section (8) sends a message to the error information reading section (9). bus slave circuit (3
-1) Request to read the error information.

The error information reading unit (9) reads the error information from the error information storage unit (6-1) of the bus slave circuit (3-1) in accordance with this request, and reads the error information from the error information storage unit (10) of the bus master circuit (1-1). Save to. In this error information storage section (10), it is stored in the format shown in FIG. 5, for example in error 1 (11-1,) in FIG. 4, or because the error occurred in the bus slave circuit at this time, Master/
The slave recognition flag (12) becomes significant, and the bus slave code in the error detection signal becomes the bus slave code (12).
3), and information indicating the actual cause of the error, for example, is stored as error information (14). For example, if an error occurs in the bus master circuit (1-1) after a two-leg error occurs, the error information is
1-2) is the master/slave recognition flag (12) shown in Figure 5.
) is saved as meaningless.

As a result of the above, the error that occurred in the bus master circuit (>1) and the bus slave circuit (3-1) will be transferred to the bus master circuit (1-1).
1) Since the errors are registered in the order in which they occur in the error information storage unit (10), the program behavior of the bus master circuit can be easily analyzed, improving the efficiency of fault search and debugging work.

In the above embodiment, the error detection signal is used to notify the error from the bus slave circuit to the bus master circuit.
This may be conveyed through a message.

Furthermore, although the case is shown in which an error is detected and data is transferred from the bus master circuit to the bus slave circuit, the error may occur during processing by the bus slave circuit due to, for example, a message from the bus master circuit.

[Effects of the Invention] As explained in 1-1 below, the present invention provides a bus master circuit with a slave card error detection section, an error information reading section, and an error information storage section, and also provides a bus master circuit with a slave card error detection section, an error information reading section, and an error information storage section, and a bus master circuit with a bus master circuit provided with a slave card error detection section, an error information reading section, and an error information storage section. Since the configuration has an error detection signal line, if an error occurs in the bus slave circuit during data transfer between the bus master circuit and the bus slave circuit, the error information is sent to the bus slave circuit. By reading out the information from the storage section and storing it in the error information storage section of the bus master circuit, it can be easily determined whether an error occurring in the bus master circuit is related to an error occurring in the bus slave circuit. Therefore, it has the effect of improving fault search and debugging efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an error information storage device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of the bus master circuit of the embodiment shown in FIG. FIG. 4 is an explanatory diagram showing an example of the error detection signal issued by the invention. FIG. 4 is an explanatory diagram showing an example of information storage in the error information storage section according to the invention. FIG. 5 is a detailed diagram showing the detailed configuration of the error information storage section. The explanatory diagram, FIG. 6, is a block diagram of a conventional error information storage device. In the figure, (1-1) to (IN) are bus master circuits,
(2) is the system bus, (3-1) to (3-M) are bus slave circuits, (11) to (1-N) are bus master code addition circuits, (51) to (5-M) are error Information generation circuits (61) to (6-M) are error information storage units, (7
) is the error detection signal line, (8) is the slave card error detection section, (9) is the error information reading section, (10) is the error information storage section, (1>1), (112)... is error information, (12) is master/slave recognition flag,
(13) is bus 1/-bukod, and (14) is error information. In addition, in the figure, the number "-n" indicates the same or a corresponding part. Agent: Patent attorney Masuo Oiwa (2 others) Written amendment (spontaneous) Hei, February 22, 1 year 5, Columns for the scope of claims and detailed description of the invention of the specification to be amended and drawings. 6. Contents of the amendment 2. Name of the invention Error information storage device 3. Person making the amendment Representative Moriya Shiki 4. Agent address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo 1.2° Scope of claims In a multi-master bus circuit configured such that multiple bus master circuits and multiple bus slave circuits are connected to a common bus, and any bus master circuit can access any bus slave circuit, the bus master circuit a slave card error detection unit that inputs an error detection signal from the bus slave circuit to the bus master circuit and receives the error detection signal to the bus master circuit when an error is detected in the bus slave circuit when accessing the bus slave circuit; , an error information reading section that reads error information from the bus slave card where an error has occurred based on information from this slave card error detection section, and an error information storage section that saves the error information read in this error information reading section. Error information storage device for circuits.

Claims (1)

[Claims] In a multi-master bus circuit configured such that multiple bus master circuits and multiple bus slave circuits are connected to a common bus and any bus master circuit can access any bus slave circuit, the bus master circuit a slave card error detection unit that inputs an error detection signal from the bus slave circuit to the bus master circuit and receives the error detection signal to the bus master circuit when an error is detected in the bus slave circuit when accessing the bus slave circuit; , an error information reading section that reads error information from the bus slave card in which an error has occurred based on information from the slave card error detection section, and an error information storage section that saves the error information read in the error information reading section. Error information storage device provided in the bus master circuit.