JPS63200248A - Memory access processing system - Google Patents

Abstract

PURPOSE:To simplify a fault processing by securing such a system where the presence of the requester information within a data array is shown regardless of the retrieving result when a fault is detected in the request information given from the requester. CONSTITUTION:The partial data stored in a main memory 300 and the address of said data are held by a data array 224 and an address array 211. A request selection means 208 selects one of the requests of the requesters 101-103 and informs it to a selection means 207. The fault detection means 201-203 detect the faults of the requests given from the requesters 101-103. If a fault is detected, a forcible hit means 220 shows a cache hit regardless of the deciding result obtained by a comparison means 212 for presence or absence of the cache hit. Then a 2nd control means 221 processes the fault in a hit process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control device having a cache memory, and particularly to an error handling method.

[Conventional technology]

This type of memory access control device is connected to multiple request sources, so even if a failure is detected in one request source, other request sources must process normally. It is configured to handle only requests for which a failure is detected.

Therefore, in conventional memory access control devices,
Even when a failure is detected in the request source, the cache memory is indexed in the same way as normal operation, and if the cache hit is detected, the error processing is executed in the hit's control circuit.

If it is a cache miss, the memory access control circuit is configured to perform error handling.

[Problem that the invention seeks to solve]

The above-mentioned conventional memory access control device.

When there is a failure in the requester's request, depending on whether the request is a hit or a mistake.

Since fault processing is handled by separate control circuits, the fault processing becomes extremely complicated and the amount of hardware increases.

[Means for solving problems]

The memory access processing method according to the present invention includes a main memory, a data array that is connected to a request source that outputs a request related to data held in the main memory, and that holds part of the data held in the main memory; An address array that holds information indicating which address on main memory the data held in the array corresponds to, and an indexing means that checks whether information requested by a request source exists in the data array.

A failure detection means for detecting a failure in requested information from a request source in a memory access control device comprising means for accessing a data array or a main memory based on an index result by an indexing means.

When the detection result of the fault detecting means indicates that a fault has been detected, the apparatus includes forcing means for indicating that the requesting information exists in the data array regardless of the result of the indexing means.

〔Example〕

Next, nine embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the present invention.
3 is a request source, 200 is a memory access control device, and 300 is a main memory (MMU).

The memory access control device 200 receives the request request source 1 through the request receiving means 204 to 206, respectively.
01 to 103, and receives requests from respective request sources.

The requests accepted by the request accepting means 204 to 206 are sent to the request selecting means 208,
Here, one of the requests is selected according to predetermined priorities and control conditions, and the first control means 21
Sent to 0.

The first control means 210 reads the contents of the address array 211 according to the address of the request source.

By indexing the address array by comparison means 212.

It is checked whether the content of the request source address exists in the data array 224, that is, whether it is a cache hit. As a result, if it is a catschhit,
The second control means 221 processes the requester's request within the data array 224 . That is, when the request source request is a store, the request source address and data selected by the request selection means 208 are
control means 210. The data sent from the request source is sent to the data array 224 through the second control means 221 and the selection means 222, and is stored at the address sent from the request source. Similarly, when reading, the address of the request source is sent to the data array 224, and the corresponding data is sent to the request source through the two selection means 225 and 226.

If the result of the index is a cache miss, the second control means 221 sends an instruction to the memory access means 223 to access the main memory 300, and the memory access means 223 accesses the main memory 300. . When the request from the request source is a read, the main memory 300 is read, and the read data is returned to the request source.
4 and register the corresponding address in the address array 211. Also, when the request is a store, the main memory 300 is read in the same way as when reading.
This time, when writing data from the main memory 300 to the data array 224, the corresponding address is registered in the address array beppin, as in the case of reading. Regardless of whether it is a read or a store, before writing data from the main memory 300 to the data array 224, if the block to be written has already been stored by human processing, the block is stored in the corresponding main memory. Write by 300 Heswanobout.

Next, we will explain the operation when there is a failure in the request from the request source. This type of memory access control device is connected to multiple request sources.

Even if a failure is detected in a request from one request source, it must be ensured that the operation of other request sources is not affected. Therefore, if there is an error in the request from the request source, the address array 211. data array 22
4. Avoid destroying the contents of the main memory 300,
The requester is configured to report that there was a failure.

In order to achieve this, conventional memory access control devices index the address array even if there is a failure in the request from the request source, and based on the result, if the hit is a cache hit, the above-mentioned control is applied to the hit. Failure handling is performed, and if it is a mistake, similar failure handling is performed in memory access control. Therefore, hardware means for handling failures as described above must be provided for both hit processing and memory access processing due to mistakes. Moreover.

Generally, memory access processing is more complex than human processing, so performing the above-mentioned fault handling in memory access processing requires a considerable investment in hardware. in this way.

Performing the above-mentioned failure processing in both hit processing and miss processing results in more complicated processing and an increase in hardware.

However, in the present invention, when the above-mentioned failure occurs, the forced hit means 220 is used.

Regardless of the request address of the request source, it is always treated as a hint, so it is only necessary to handle the error using hit processing, and the above-mentioned error processing in conventional error handling is not required, making the processing easier and requiring less hardware. I'll try it.

Next, failure handling in two embodiments of the present invention will be explained in detail.

Requests from request sources 101-103 are accepted by request accepting means 204-206, and at the same time, failures are checked by failure detecting means 201-203. When a request source is selected by the request selection means 208, the failure detection means connected to the same request source is selected by the selection means 207, and it is known whether or not there is a failure in the request from the request source.

The request selected by the request selection means 208 is sent to the first control means 210, and is sent to the address array 211. Comparison method 2
12, it is determined whether or not there is a catch hit.

However, this time.

If a failure of the request source request is detected in the output of the selection means 207, the forced hit means 220 indicates a catch hit based on the result of the comparison means 212, and the second control means 221
send to

The second control means 221 performs the above-mentioned fault processing in the hit processing based on the fault report and cash hit signal.

In this way, the failure of the requesting request.

Failure processing will always be performed using catch hit processing only.

〔Effect of the invention〕

As explained above, in the present invention, when a fault in a request source request is detected, by setting the state to be the same as a cash hit, the above fault processing is not only performed in the hit processing, but also the above mentioned fault processing in the memory access processing due to a mistake is performed. This eliminates the need for failure handling, which has the effect of simplifying the processing and reducing the amount of hardware required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 101-103...Request source, 200...Memory access control device, 300...Main memory, 201-2
03... Fault detection means, 204-206... Request reception means, 207... Selection means, 208... Request selection means, 210... $1 control means, 2
11... Address array, 212... Comparison means, 2
20... Forced hit means. 221... Second control means, 222... Selection means,
223...Memory access means, 224...Data array. 225, 226...Selection means.

Claims (1)

[Claims] 1. A main memory and a data array connected to a request source that outputs a request related to the data held in the main memory and holding a part of the data held in the main memory, and a data array held in the data array. an address array that holds information indicating which address on the main memory the data corresponds to; an indexing means for checking whether the information requested by the requester exists in the data array; and an indexing result obtained by the indexing means. A memory access control device comprising: a means for accessing the data array or the main memory according to the method; a fault detection means for detecting a fault in requested information from a request source; and a fault detection means based on a detection result of the fault detection means. and a forced hit means for indicating that the requesting information existed in the data array regardless of the result of the indexing means.