JPS61160164A - Information processor - Google Patents

Abstract

PURPOSE:To minimize the number of IC chips to be replaced even when retrial succeeds by by-passing a buffer storage to access a main storage when the fault is detected at the reading of data from the buffer storage. CONSTITUTION:If a fault is detected in data read out from the buffer storage 4, the fault is informed to a buffer storage control part 2 through a signal line 107 and then informed to a data processing part 7 through a signal line 113. Only when a fault is detected in the data read out from the main storage or the buffer storage 4 a fault detecting circuit 8 validates the information on the signal lines 107, 113. When a fault is detected at the reading of data from the main storage, the fault is informed to a fault processing control part. When the error information is informed through the signal line 107, the buffer storage control part 2 sends a main storage reading request to a main storage access control device 1 and resets a corresponding flag in a buffer storage valid display flage storing part 3. Then, the read data from the main storage are compared with that from the buffer storage and the compared result is held.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device having buffer storage.

(Prior Art) Conventionally, in this type of information processing device, even if a fault is detected by reading data from a buffer memory, error information is immediately generated and the fault processing control unit is notified of the fault. It was configured so that At this time, if retry is possible, retry can be performed.

(Problem to be solved by the invention) However, when an intermittent failure occurs, it is difficult to point out which IC chip should be replaced, so all related IC chips must be replaced. was there.

An object of the present invention is to bypass the buffer memory and access the main memory when a failure is detected when reading data from the buffer memory, read the corresponding data from the main memory, and Compare the continued data with the data from the main memory above, retain the comparison result, and reset the valid display flag of the corresponding area of the sofa memory (above). To provide an information processing device configured to minimize the number of IC chips to be replaced even if a trial is successful.

(Means for Solving the Problems) An information processing device according to the present invention includes a buffer storage, a buffer storage valid display flag storage unit, a buffer storage control unit, a selector, a register, a failure detection circuit, and a data processing unit. It is constructed by comprising a section.

Buffer storage is for temporarily storing main memory data.

The buffer storage validity display flag storage section is for setting flag information indicating whether or not requested data is correctly stored in the buffer storage.

The buffer storage control unit controls the reading of the requested data from the buffer storage when the requested data is stored in the buffer storage, and controls reading of the requested data from the buffer storage when the requested data does not exist. This is to control writing of the data into buffer storage.

The selector is for switching between the contents of the buffer storage and the main storage data based on an instruction from the buffer storage control section.

The register is used to temporarily store the output of the selector.

The fault detection circuit is for detecting faults present in the contents of the registers.

If a fault is detected by the fault detection circuit when reading data from the buffer memory, the data processing unit bypasses the buffer memory and accesses and reads the main memory, thereby processing the read data from the main memory. This is to instruct the buffer storage control unit to compare the data read from the buffer storage, hold the comparison result, and reset the flag information.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, the information processing apparatus of the present invention includes a main memory access control device 1, a buffer storage control section 2, a buffer storage validity display flag storage section 3,
It is composed of a buffer memory 4, a selector 5, a register 6, a data processing section 7, and a failure detection circuit 8.

In FIG. 1, a main memory read request from the data processing section 7 is normally notified to the buffer storage control section 2 through a signal line 108. The buffer storage control section 2 reads the contents of the buffer storage validity display flag storage section 3 and checks whether the requested data exists in the buffer storage 4 or not. I (If the requested data exists in the sofa memory 4, read the data from the buffer memory 4 and pass the read data to the data processing unit 7 through the selector 6 and register 6. does not exist, the buffer storage control unit 2 connects the signal line 10
A data read request is sent to the main memory access control device 1 through 0. Therefore, a data reply signal is sent from the main memory access control device 1 onto the signal line 101, and the buffer storage control unit 2 receives it. Next, the buffer storage control section 2 writes the read data on the signal line 109 into the buffer storage 4 and passes the read data to the data processing section 7 through the 1 selector 5 and the register 6.

Furthermore, at this time, the buffer storage valid display flag storage unit 3
Sets a display flag to indicate that the data at the corresponding address is valid.

When a failure is detected in the data read from the buffer storage 4, the information processing section 7 operates as follows. That is, when a fault in the data included in the contents of the register 6 is detected by the fault detection circuit 8 via the output signal line 112, the fault is notified to the buffer storage control unit 2 via the signal line 107, and further signal line The data processing unit 7 is notified via 113. The fault detection circuit 8 validates the information on the signal lines 107 and 115 only when a fault is detected in the data read from the main memory or buffer memory.

If a failure is detected during subsequent access from the main memory, the failure is notified to a failure processing control unit (not shown). When error information is notified through the signal line 107, the buffer storage control unit 2 sends a main memory read request to the main memory access control device 1, and also sends a buffer storage valid display flag storage unit 3.
Reset the appropriate flags.

Next, the operation of the data processing section 7 when error information is notified on the signal line 11a will be explained with reference to FIG.

In FIG. 2, one embodiment of the data processing section 1 includes a microprogram control section 11 and a scratch pad memory 12.
, a register 16.18, an arithmetic circuit 14, and a selector 15.17.

In FIG. 1, when error information is notified through the signal line 113, data for a mode in which the error information is ignored is input to the data processing unit 7 through the signal line 112, and is passed through the selector 17 shown in FIG. 2 to the register 18. is set to

Next, the cache access address signal at this time is applied to the selector 15 via the signal line 103, and is set in the register 16 via the selector 1. The contents of register 16 are then written to scratchpad memory 12 via signal line '209. Thereafter, data is read from the main memory in the buffer storage control unit 2, and the read data is set in the register 16 via the selector 15. After that, the arithmetic circuit 14 calculates the exclusive OR of the outputs of the registers 18 and 18, and the arithmetic result is sent to the selector 15.
It is set in the register 16 through the process. The contents of register 16 are then written to scratchpad memory 12.

Therefore, the data in the mode of ignoring error information is canceled. The contents of the scratchpad memory 12 are notified to the fault data collection device f (not shown) via a communication means, so if the data is collected and stored, it can be used for later data analysis. can.

(Effects of the Invention) As explained above, the present invention has the following advantages: When a failure is detected while reading data from the buffer memory, the main memory is accessed and the data is read, and the valid display flag of the buffer memory is set. This has the effect of minimizing the number of chips to be replaced in the event of an intermittent failure by resetting, comparing the data read from the main memory and the data read from the buffer memory, and retaining the comparison results.

[Brief explanation of drawings]

FIG. 1 is a block diagram partially showing an embodiment of an information processing apparatus according to the present invention. FIG. 2 is a block diagram showing details of the data processing section shown in FIG. 1. 1... Main memory access control device 2... Buffer memory control section S... Buffer memory valid display flag storage section 4... Buffer memory 5... Selector 6.16.18... Register 8. ...Fault detection circuit 11...Microprogram control unit 12...Scratch pad memory 14...Arithmetic circuit 16.17...Selector

Claims (1)

[Claims] a buffer memory for temporarily storing main memory data; a buffer memory valid display flag storage unit for setting flag information indicating whether or not requested data is correctly stored in the buffer memory; If the requested data is stored in the buffer storage, the requested data is controlled to be read from the buffer storage, and if the requested data does not exist, it is read out from the buffer storage. a buffer storage control unit for controlling writing to memory; a selector for switching between the contents of the buffer storage and the main storage data according to an instruction from the buffer storage control unit;
a register for temporarily storing the output of the selector; a fault detection circuit for detecting a fault existing in the contents of the register; and a fault detection circuit for detecting a fault when reading data from the buffer storage. If the fault is detected, the data read from the main memory is compared with the data read from the buffer memory by bypassing the buffer memory and accessing and reading the main memory, and the result of the comparison is and a data processing unit for instructing the buffer storage control unit to hold the flag information and reset the flag information.