JPH01191941A - Information processor - Google Patents

Abstract

PURPOSE:To increase the processing speed for an instruction which is processed as an exception by using a means which detects a foul field of an instruction word and a means which suppresses the access request of the instruction word to a memory when the foul field is detected by said detecting means. CONSTITUTION:In case a vector instruction is set at an instruction register 1, a test circuit 5 checks the vector instruction permission bit of a system control register 4. If said permission bit is equal to '0', the circuit 5 detects a foul field. Then a request suppressing circuit 6 sets a request key signal '0' at a request code register 8. While a foul field detecting signal '1' is set at a flip-flop 9.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and particularly to an information processing device that handles an instruction as an invalid field when the instruction does not meet a preset condition depending on the type of the instruction. .

Conventionally, in this type of information processing device, illegal fields, that is, the value of a specific field of an instruction word, the value of a register specified by a specific field of an instruction word, or the value of a specific register unrelated to an instruction word, Regardless of whether an instruction whose value differs from a predetermined value occurs or not, the memory request for this instruction is always sent to the memory buffer control unit in the same way as when no invalid field occurs. .

Therefore, for an instruction in which an invalid field occurs, after the memory request for the instruction is processed by the memory buffer control unit, the invalid field is detected by the microprogram control unit and exception processing is performed.

In such a case, the instruction itself is subject to exception handling, so the result of the memory request processed by the memory buffer control unit is not used at all.

In addition, in memory request processing in the memory buffer control unit, the instruction that requested the memory request itself becomes an exception, so the address translation buffer that converts the logical address of the memory request into a physical address is There is almost no possibility that the address conversion information is registered in advance, and it is also extremely unlikely that the memory data itself corresponding to this memory request is registered in the cache memory.

Therefore, after performing index processing on the segment table and page table to obtain a physical address for address conversion in a memory request of an instruction that is an exception handling, memory data is retrieved from the main storage address corresponding to this physical address. It was being read.

Furthermore, the address translation information obtained by indexing the segment table and page table is automatically registered in the address translation buffer. Data will be removed from one and this address conversion information will be registered there.

Memory data read from the main memory is also automatically registered in the cache memory after being read from the main memory in the same manner as the processing in the address translation buffer described above, and empty blocks in the cache memory are If not, the data will be evicted from one of the used blocks and this memory data will be registered there.

In such conventional information processing devices, regardless of whether an invalid field occurs or not, the memory request for this instruction is always sent to the memory buffer control unit in the same way as when no invalid field occurs. This has disadvantages in that the time required for memory request processing in the memory buffer control unit results in loss time, and the processing speed of instructions used for exception processing is reduced.

Additionally, as address translation information and memory data are registered in the address translation buffer and cache memory as memory request processing for instructions that result in exception processing in the memory buffer control unit occurs, the usage efficiency of the address translation buffer and cache memory decreases. This has the disadvantage of causing a decrease in the performance of the device itself.

The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and can improve the processing speed of instructions that are exception handling, and reduce the efficiency of using address translation buffers and cache memory. An object of the present invention is to provide an information processing device that can improve the performance of the device without causing problems.

An information processing apparatus according to the present invention is an information processing apparatus that performs exception processing as an invalid field when a condition of an instruction word including an instruction code does not match a preset condition according to the instruction code. and a detection means for detecting an invalid field in the instruction word; and a suppressing means for suppressing a memory access request by the instruction word when the detection means detects the invalid field. .

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG.
, register memory (BR) 3, system control register (SCR) 4, test circuit 5, request suppression circuit 6, and microprogram address register (MAR).
7, a request code register (RCR) 8, and a flip-flop (FF) 9.

The instruction register 1 holds an instruction word including an instruction code, a register number serving as an operand, and a pace register number used to calculate the address of the operand.

The instruction code held in instruction register 1 is on signal line 1
The register number is output to the test circuit 5 via the signal line 102, and the pace register number is output to the register memory 3 via the signal line 103.

The instruction code decoder 2 is indexed by the instruction code from the instruction register 1 input via the signal line 101.

Using this index, the start address of the microprogram that processes the given instruction code is output to the microprogram address register 7 via the signal line TO4, and a request indicating the type of memory request for processing the given instruction code is output to the microprogram address register 7 via the signal line TO4. The code is output to the request code register 8 via the signal line 105.

Further, a request representative signal indicating the presence or absence of a memory request is output to the request suppression circuit 6 via the signal line 106, and an exception detection instruction signal for detecting an invalid field is output to the test circuit 5 via the signal line 107. Ru.

The register memory 3 stores pace registers used to calculate operand addresses, and the most significant bit is output to the test circuit 5 via the signal line 108 in response to input of the pace register number from the instruction register 1.

The state of the vector instruction permission bit is output from the system control register 4 to the test circuit 5 via the signal line 109.

The test circuit 5 tests the value of the instruction register 1, the value of the register memory 3, and the value of the system control register 4 in response to the exception detection instruction signal from the instruction code decoder 2, detects an invalid field, and results in the detection. is output to the request suppression circuit 6 and the flip-flop 9 via the signal line 110, respectively.

When the test circuit 5 does not detect an invalid field, the request suppression circuit 6 outputs the request representative signal from the instruction code decoder 2 as it is to the request code register 8 via the signal line 111.

Further, when the test circuit 5 detects an invalid field, the request suppression circuit 6 transmits the value "0" to the signal line 111.
It is output to the request code register 8 via.

The microprogram address register 7 holds the start address of the microprogram from the instruction code decoder 2, and the request code register 8 holds the request code indicating the type of memory request from the instruction code decoder 2 and the request code from the request suppression circuit 6. The request representative signal is held.

The flip 70 tab 9 displays the detection result in the test circuit 5, that is, whether or not the test circuit 5 detected an invalid field.

The output signals from the microprogram address register 7 and the flip-flop 9 are output to a microprogram control section (not shown), and the request code register 8
The output signal is output to a memory buffer control section (not shown).

FIG. 2 is a block diagram showing a detailed configuration of the test circuit 5 in FIG. 1. In FIG. There is.

Not gates 51 and 52 receive the exception detection instruction signal bit 0.0 from the instruction code decoder 2. Bit 1 is inputted, and the inverted value thereof is outputted to AND gates 54 and 55.

Furthermore, the NOT gate 53 inputs the state of the vector instruction permission bit from the system control register 4 and outputs its inverted value to the AND gate 56 .

The AND gate 54 inputs the exception detection instruction signal bit 1 of the two instruction code decoders, the exception detection instruction signal from the NOT gate 51, the inverted value of bit 0, and the register number from the instruction register 1. A logical AND operation is performed and the result of the operation is output to the OR gate 57.

The AND gate 55 inputs the exception detection instruction signal bit 0 from the instruction code decoder 2, the inverted value of the exception detection instruction signal bit 1 from the NOT gate 52, and the most significant bit from the register memory 3. A product operation is performed and the result of the operation is output to the OR gate 57.

The AND gate 56 receives the exception detection instruction signal bit 0.0 from the instruction code decoder 2. Bit 1 and the inverted value of the state of the vector instruction permission bit from the NOT gate 53 are input, a AND operation is performed on them, and the result of the operation is output to the OR gate 57.

That is, the exception detection instruction signal from the instruction code decoder 2 is "01" (bit 0 is "0", bit 1 is "1").
”), the register number from instruction register 1 (
When the least significant bit of the register number of the operand register is "1", the invalid field detection signal outputted via the signal line 110 becomes "1".

Also, the exception detection instruction signal from the instruction code decoder 2 is “10” (bit 0 is “1” and bit 1 is “0”).
), when the most significant bit from the register memory 3 is "1", the invalid field detection signal outputted via the signal line 110 becomes "1".

Furthermore, when the exception detection instruction signal from the instruction code decoder 2 is "11" (both bit 0 and bit 1 are "1"), when the vector instruction permission bit from the system control register 4 is "O", the signal line The invalid field detection signal outputted via 110 becomes "1".

FIG. 3 is a block diagram showing a detailed configuration of the request suppression circuit 6 of FIG. 1. In FIG. 0, the request suppression circuit 6 is composed of a NOT gate 61 and an AND gate 62.

The NOT gate 61 inputs the invalid field detection signal from the test circuit 5 via the signal line 110, and outputs its inverted value to the AND gate 62.

The AND gate 62 performs an AND operation between the request representative signal from the instruction code decoder 2 inputted via the signal line 106 and the inverted value of the invalid field detection signal from the NOT gate 61, and calculates the result of the operation. Output to request code register 8.

That is, when the invalid field detection signal from the test circuit 5 is "0", the request representative signal from the instruction code decoder 2 is directly sent to the request code register 8.
When the invalid field detection signal from the test circuit 5 is "1", the value "O" is output to the request code register 8, indicating that there is no memory request.

FIG. 4 is a diagram showing the conditions under which an invalid field occurs. In the case of a "double load instruction," an invalid field is detected when the register number of the general-purpose register to be loaded is not an even number.

Further, in the case of a "stack control instruction", an invalid field is detected when the most significant bit of the pace register used in calculating the address of the top of the stack is not "0".

Further, in the case of a "vector instruction", an invalid field is detected when the vector instruction permission bit of the system control register 4 is not "1".

FIG. 5 is a flowchart of a microprogram in one embodiment of the present invention. The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 5.

In the exception detection instruction field of instruction code decoder 2, "01" is in the field of the word to decode the "double load instruction", "10" is in the field of the word to decode the "stack control instruction", and "10" is in the field of the word to decode the "stack control instruction". The field of the word that decodes the “instruction” is “11”.
”, but “00” is written in advance in the fields of instructions in which no invalid fields occur.

When a “double load instruction” is set in the instruction register 1, the start address of the microprogram that processes the “double load instruction” is output from the instruction code decoder 2 to the microprogram address register 7 via the signal line 104. be done.

Further, a request code indicating the type of memory request is output to the request code register 8 via the signal line 105, and a request representative signal is output to the request suppression circuit 6 via the signal line 106 to indicate that there is a memory request. be done.

Furthermore, in order to instruct the test circuit 5 to detect an invalid field, "01" written in the exception detection instruction field of the instruction code decoder 2 is output to the test circuit 5 via the signal line 107. .

In accordance with the exception detection instruction signal from the instruction code decoder 2, the test circuit 5 checks the register number of the operand indicated by the instruction word set in the instruction register 1, and if this register number is not an even number, that is, the register of the operand register If the least significant bit of the number is "1", the value "1" is output as an invalid field detection signal to the request suppression circuit 6 and the flip-flop via the signal line 11G (step 11 in FIG. 5).

When the request suppression circuit 6 receives the value "1" as the invalid field detection signal from the test circuit 5, it outputs the value "0" as the request representative signal to the request code register 8.

Therefore, the memory request for the "double load instruction" set in instruction register 1 is sent to the memory buffer yili.
It is not output to the lJl1 section, but the microprogram control section contains the start address of the microprogram that processes the "double load instruction" stored in the microprogram address register 7, and the test value set in the flip-flop 9. 1" is sent, and this "double load instruction" is treated as an invalid field and exceptional processing is performed by the microprogram control unit (step 14 in FIG. 5).
).

In addition, in test time [5], if the register number of the operand indicated by the instruction word set in instruction register 1 is an even number, that is, if the lowest bit of the register number of the operand register is "O", the invalid field detection signal is The value “0” is sent to the request suppression port v via the signal line 110.
@6 and the flip-flop 9 (step 11 in FIG. 5).

When the request suppression circuit 6 receives the value "0" as the invalid field detection signal from the test circuit 5, it outputs the request representative signal "1" from the instruction code decoder 2 as it is to the request code register 8.

Therefore, the memory request for the "double load instruction" set in the instruction register 1 is output to the memory buffer control section, and the memory request for the "double load instruction" stored in the microprogram address register 7 is output to the microprogram control section. The start address of the program and the value “0” indicating that no invalid field was detected by the test circuit 5 set in the flip-flop 9.
is sent.

The microprogram control unit executes the memory request of this "double load instruction", waits for the memory data to be delivered from the memory buffer control unit (step 12 in Figure 5), and executes the instruction using the memory data. Processing is performed (step 13 in FIG. 5).

When the "stack control instruction J" is set in the instruction register 1, the start address of the microprogram that processes the "stack control instruction" is sent from the instruction code decoder 2 to the microprogram address register 7 in the same manner as described above. A request code indicating the type of memory request is output to the request code register 8, and a request representative signal is output to the request suppression circuit 6 to indicate that there is a memory request.

Further, in order to instruct the test circuit 5 to detect an invalid field, "10" written in the exception detection instruction field of the instruction code decoder 2 is output to the test circuit 5 via the signal line 107.

In accordance with the exception detection instruction signal from the instruction code decoder 2, the test circuit 5 checks the most significant bit of the pace register used to calculate the operand address indicating the top of the stack, and determines that this most significant bit is “0”.
If so, the request representative signal '1' is set in the request code register 8, and the illegal field detection signal '0' is set in the flip-flop 9.

Therefore, the memory request processing of this instruction by the memory buffer control section and the execution processing of this instruction by the microprogram control section are performed.

However, the most significant bit of the pace register is “1”
If so, the test circuit 5 detects an invalid field,
A request representative signal "0" is set in the request code register 8, and an invalid field detection signal "1" is set in the flip-flop 9.

Therefore, this "stack control instruction" is treated as an invalid field and exceptional handling is performed by the microprogram control unit.

Even when a "vector instruction" is set in the instruction register 1, the instruction code decoder 2
“11” written in the exception detection instruction field is output to the test circuit 5 via the signal line 107.

The test circuit 5 checks the vector instruction enable bit of the system control register 4 in accordance with the exception detection instruction signal from the instruction code decoder 2, and if the vector instruction enable bit is "1", the request code register 8 is A request representative signal "1" is set, and an invalid field detection signal "0" is set in the flip-flop 9.

Therefore, the memory request processing of this instruction by the memory buffer control section and the execution processing of this instruction by the microprogram control section are performed.

However, if the vector instruction permission bit of the system control register 4 is “O”, the test circuit 5 detects an invalid field, the request representative signal “0” is set to the request code register 8, and the flip-flop 9 is set to the invalid field. Field detection signal "1" is set.

Therefore, this "vector instruction" is treated as an invalid field and exceptional processing is performed by the microprogram control unit.

In this way, when an invalid field of an instruction word set in the instruction register 1 is detected in the test circuit 5, the request suppression circuit 6 suppresses a memory request for the instruction word, thereby making it possible to control the microprogram control unit. In this case, when an invalid field is detected, it becomes possible to immediately perform exception processing without performing unnecessary memory request processing in the memory buffer control unit.

Furthermore, in the memory buffer control unit, the address translation buffer and cache memory are not disturbed by unnecessary memory request processing.

Therefore, it is possible to improve the processing speed of an instruction that is an exception process, and it is possible to improve the performance of the device without reducing the efficiency of using the address translation buffer and cache memory.

In one embodiment of the present invention, the conditions for generating an invalid field include a "double load instruction" and a "double load instruction" as shown in FIG.
Although the examples of "stack control instruction" and "vector instruction 1" have been described, it is obvious that the present invention can also be applied to cases where an illegal build occurs in other instructions, and is not limited thereto.

1 Suctioned Bean 1 As explained above, according to the present invention, when an invalid field is detected in an instruction word including an instruction code, in which the conditions of the instruction word do not match the conditions set in advance according to the instruction code. By suppressing memory access requests using this instruction word, it is possible to improve the processing speed of instructions that are exception handling, and to improve the processing speed of instructions that are used for exception processing, without reducing the efficiency of using address translation buffers and cache memory. This has the effect of improving the performance of.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the detailed configuration of the test circuit in FIG. 1, and FIG. 3 is a block diagram showing the detailed configuration of the request suppression circuit in FIG. FIG. 4 is a block diagram showing the configuration, FIG. 4 is a diagram showing the conditions under which an invalid field occurs, and FIG. 5 is a flowchart of a microprogram in an embodiment of the present invention. Explanation of symbols of main parts 1...Instruction register 2...Instruction code decoder 3...Register memory 4...System control register 5...・Test circuit 6...Request suppression circuit

Claims (1)

[Claims] (1) An information processing device that performs exception processing as an invalid field when a condition of an instruction word including an instruction code does not match a preset condition according to the instruction code,
Information processing comprising a detection means for detecting an invalid field in the instruction word, and a suppression means for suppressing a memory access request by the instruction word when the detection means detects the invalid field. Device.