JPS63752A - Memory protection system - Google Patents

Abstract

PURPOSE:To ensure protection of a memory not only in a mapping mode but also in a direct mode by latching an effective ring level RLE and comparing it with a reference ring level RLR. CONSTITUTION:A selection circuit 10 selects the RLR of a latch circuit 7 and the RLE of a latch circuit 6 when a mode flag 12 in a program state PSW1 designates a mapping mode and a direct mode respectively to use it as the comparison input at one side of a comparator 9. The other comparison input of the comparator 9 is always equal to the RLE of the circuit 6. Therefore, access is given to a main memory with no limit in case RLE=0 is satisfied in the mapping mode. The access of the main memory is complied with access control information AR in case of RLE<=RLR and the access is possible only with reading in case of RLE>RLR. While in the direct mode the conditions are always secured for RLE=RLR and the memory protection is limited in accordance with the access information AR.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a memory protection system for electronic computers.

In detail, access to the main memory is protected using ring levels and access restrictions, and information on the ring levels and access restrictions is stored in an address translation table, and the ring level (reference ring level) and program information held in the address translation table are A memory protection method in a computer that controls the restriction conditions of access restriction information by comparison with the ring level (execution ring level) on the state word (p sw) [Prior art] Conventional technology in this type of computer The memory protection method will be explained with reference to FIG.

Figure 5(a) shows the ring level (RL) and access restrictions (
This is an example implemented by DIPS, etc., which performs memory protection using AR). 1 is the program state m <
p s w ), and 11 indicates the execution ring level (RLE) within the PSW. 2 is the logical address of the operand etc. to be referenced, segment number S, page number P,
Contains in-page address L, 3 is segment base register (SBR), 4 is segment table (ST)
, 5 is a page table (PT). The segment base register 3 holds the start address of the segment table 4, and adds the S field in the logical address 2 to this to access the segment table 4 and obtain the page table address. The P field in logical address 2 is added to this page table address to access page table 5.

Get the page address. A real address is determined by joining the L field in logical address 2 to the lower order of this obtained page address. The corresponding entry in the segment table 4 holds a reference ring level (RLR) 41, and the corresponding entry in the page table 5 holds access restriction information (A
R) is retained.

The latch circuit 6 receives the effective ring level (RL) from the PSWI.
E) is received. The latch circuit 7 also receives the reference ring level (RLR) read from the segment table 4. The comparison circuit 8 determines whether RL is O or not, and the comparison circuit 9 determines the magnitude relationship between RLE and RLR. R.L.
, =O, the value of the access restriction information (AR) read from the page table 5 is not affected, and no restriction is applied to memory access. When RLI:≦RLR, it depends on the content of access restriction information (AR). That is, in the case of RL, )RLR, only operand read access is allowed.

FIG. 5(b) shows the relationship between the above-mentioned RL, RLR, and access restriction. Figure 5(c) shows the access restriction information (AR
) is an example of the content.

[Problem that the invention seeks to solve]

As mentioned above, when protecting access to main memory using the ring level and access restrictions, in the conventional technology, memory protection using the ring level is performed at the execution ring level (RLE).
) and the concept of reference ring level (RLR). In this case, the execution ring level (RLE) is P
On the SW, the reference ring level (RLR) is held on the address translation table, so the protection mechanism operates only in the mapping mode that indexes the address translation table.
The drawback was that full thermal memory protection was not performed in direct mode.

Further, access restriction (AR) in units of logical pages is also held only in the address conversion table, and the unit of protection is a relatively large capacity unit of page. However, programs also run in the direct mode, and in particular, most programs that want to minimize unnecessary processing, such as a virtual machine monitor (VM monitor), run in the direct mode. Therefore, a memory protection mechanism is required during direct mode.There are cases where a relatively large capacity unit such as a page is handled, and there are cases where smaller capacity data is handled, so memory protection in small capacity units is necessary. requested.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory protection method that eliminates the above drawbacks in a computer that protects memory using ring levels and access restrictions.

[Means and effects for solving the problems] The present invention provides that, in the mapping mode, the reference ring level (RLII) of the address translation table and the execution ring level (RLII) on the PSW are
RLE), when RLE=0, there is no restriction access, and when RL or ≦RL3, according to the access restriction information,
In addition to the control mechanism that allows only reading when RLE>RLR, in direct mode, the execution ring level (RL
The main idea is to provide a control mechanism that always makes E) equal to the reference ring level (RLR) so that memory protection can be effectively operated in both mapping mode and direct mode.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The difference from FIG. 5 is that a selection circuit 10 is added. During PSWI, in addition to the execution ring level (RLE),
A mode flag 12 indicating whether the mode is direct mode or mapping mode is included. The latch circuit 6 latches the effective ring level (RLE) of PSWI, and the latch circuit 7 latches the reference ring level (RLE) read from the segment table 4.
RLR) 41 is latched. Although omitted in FIG. 1, access restriction information (AR) is read from the page table in the process of address translation. Comparison circuit 8 is RL.

The comparator circuit 9 determines the magnitude relationship between RLE and RLR.

The selection circuit 1o selects the RLR of the latch circuit 7 when the mode flag 12 in the PSWI specifies the mapping mode.
When the direct mode is specified, this circuit selects RLE of the latch circuit 6 and uses it as one comparison input of the comparison circuit 9. The other comparison input of the comparison circuit 9 is always the RL of the latch circuit 6. Therefore, in mapping mode, the same logic as in Figure 5 is performed, and RLE=
When O, main memory is accessed without restriction, RL, ≦R
At the time of LR, follow the access restriction information (AR), RLE>
In the case of RLR, only read access is possible.

- On the other hand, in the direct mode, the condition of RLE=RL, l is always created, and memory protection is restricted according to access restriction information (AR).

FIG. 2 is a block diagram of another embodiment of the present invention, which holds access restriction information for each real page in the main memory in addition to the access restriction information (AR) on the address translation table. This is an example in which a first memory is used to store access restriction information for a small unit capacity within the real page, and a second memory is used to hold access restriction information for the small unit capacity within the real page. In Figure 2, 101, 10
2 is a processor, 131 is a memory access control unit, 14
is the main memory. 20 is a first memory (ARMI) which has access restriction information corresponding to the real page of the main memory, in addition to the access restriction information (AR) on the address translation table.
), 21 is a second memory (ARM2) having access restriction information in small unit capacity units within the relevant real page. 22 is a real address.

The memory 20.21 is read using the real address 22 when accessing the main memory 14. Since the memory 21 is an address within a page, by decoding the bit of the L part of the real address 22, the number of small unit capacity units within the page is determined.

Reads the access restriction information for the small capacity unit.

FIG. 3 shows a memory protection control mechanism based on the two-stage access restriction information shown in FIG. In fig.

Reference numeral 25 indicates access restriction information read from the first memory 20 (ARMI), and 26 indicates access restriction information read from the first memory 20 (ARMI).
The access restriction information read from M2) is shown. 25
1 is the first bit in the information 25 and indicates whether or not the access restriction information in ARMI is used. When 251 is “○”, access restriction information 252 in ARMI is used, and I
At the time of t I II, AR retains access restriction information for each smaller unit of the page, not the information in ARMI.
Use information 26 in M2. There are 2m pieces of access restriction information 26 per page in the ARMZ. The small unit capacity unit is obtained by extracting m bits from the intra-page address L part of the real address 22 and decoding it with the decoder 23.

The latch circuit 27 holds the first bit 251 of the access restriction information 25 read from the ARMI, and the selection circuit 30
selects whether to use the information 25 from ARM1 or the information 26 from ARM2 depending on the contents of the latch circuit 27.
The access restriction information selected by the selection circuit 30 is held in the register 31. The AND circuit 32 performs an AND operation between the access restriction information read from ARMI or ARM2 of the register 31 and the access restriction information held in the page table 5, and transmits the AND result to the register 33.
to hold.

The selection circuit 34 selects the register 3 through a signal line 121 indicating the contents of the mapping/direct mode flag of the PSW.
3, or use the AR of register 31.
This is a circuit that selects whether to use the access restriction information read from MI or ARM2 as is, and selects the contents of register 33 in mapping mode, and selects the contents of register 31 in direct mode.9 Selection circuit 4 The information selected in is registered in the address translation buffer (ATB) via the signal line 341. - On the other hand, the determination circuit 35 performs a determination to detect a memory protection exception in response to a request (Req) to the memory, and if a memory protection exception is detected, memory access is inhibited and the program interrupt of the memory protection exception is executed. wake up

FIG. 4 is a block diagram of a part that registers access restriction information in an address translation buffer (ATB) when protecting a small capacity unit, thereby realizing high-speed address translation and memory protection exception detection. 40° 41 is the address translation buffer (ATB), 42 is an example of the contents of one entry in the ATB,
LA is a logical address, P is a real page number, and RL is a ring level.

AR' is access restriction information generated as shown in FIG. 3, sent from the signal line 341, and registered. Conventionally, AR' stores the contents read from the page table, but since the access restriction information generated in FIG. 3 has a different value from the AR from the page table, it is written as AR'. 421 indicates whether or not the page is protected for a small amount, and the same content as 251 in FIG. 3 is stored.

422 is the unit number of the small capacity unit.

Information from ATB 40.41 is latched into latch circuits 43-48. The comparison circuit 51 compares the logical address 2 such as the operand address with the physical address (LA) of the effect memory 42 in the ATB, and the comparison circuit 52 compares the small capacity unit designation number of the address in the page of the logical address 2 with the corresponding unit number in the ATB. 422 is confirmed. The AND gate 53 is a gate that indicates whether or not to output the comparison result of the comparison circuit 52 according to the contents of the ATB internal information 421.
When the content of 421 is Lg I H, the comparison result of the comparison circuit 52 (signal of 0 or 1) is sent to the AND gate 54, and when the content of 421 is "□ jl, the comparison result of the comparison circuit 52 is sent to the AND gate 54. Since it is meaningless, the output of the AND gate 53 is always "0" and only the output value of the AND gate 55 is valid.
“1” if there is a match and the content of 421 is “0”
This is the result. Note that when the content of 421 is "1", the AND gates 53 and 54 take the AND condition of the comparison result output of the comparison circuit 51 and the comparison result output of the comparison circuit 52, and 1, both are the information in the ATB. Only when they match, the real page number (P), ring level (RL), and access restriction information (AR') output from the ATB become valid. Selection circuits 57 to 59 determine whether the information is valid or invalid.
is selected.

A detailed explanation regarding the index of the address translation buffer (ATB) will be omitted since it is generally known.

Also, in the address translation buffer (ATB).

Even when memory is accessed in tie-left mode, protection information (such as RLRAR) may be registered to speed up processing. At that time, the ATB entry holds and identifies whether the information is for direct mode or not. When the present invention is applied to this, the RL of the information registered in the direct mode may be the RLE generated in FIG. 1, or may be a different value.

〔Effect of the invention〕

As described above, according to the present invention, in an electronic computer that protects memory by ring level and access restriction, memory can be protected not only in mapping mode but also in direct mode. In addition, by having two sides of access restriction information for real pages and access restriction information for small page capacity units, access control for small page capacity units can be applied in both mapping mode and direct mode. As a result, it becomes possible to create programs with high reliability, and it also becomes easier to create programs that process in direct mode in order to reduce the number of steps in the program, and the performance of the device can be improved.

Furthermore, by registering the unit number in the address translation buffer (ATB) for protection in small capacity units, high-speed address translation is possible even when protection is performed in small capacity units. As a result, ATB changes from allocation in page units to allocation in 1/2 m page units, and ATB
The probability that the RAM is not on the TB will increase, and the performance will drop to some extent. However, due to the high integration of the RAM elements used in the ATB, the capacity of the ATB is increasing, so the ATB can be used more effectively.
TB can be used, and the impact on performance is considered to be minimal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention regarding ring level control around PSW, FIG. 2 is a block diagram of an embodiment of the present invention in which access restriction information is provided in two stages, and FIG.
FIG. 4 is a block diagram of an embodiment of the present invention regarding memory protection control using step-by-step access restriction information.
FIG. 5 is a block diagram of an embodiment of the present invention regarding control of information retention and reference to B), and FIG. 5 is a diagram showing an example of the configuration of a conventional memory protection system. 1...Program status word (PSW), 11...Execution ring level (RL), 12...Direct/mapping mode latch. 2...Logical address, 4, 5...Address conversion table , 41... Reference ring level (RLR), 5
1... Access restriction information (AR), 8.9... Comparison circuit, 10... Selection circuit, 20.21... Access restriction information holding memory, 22... Real address, 40
．． 41...Address translation buffer. Figure 1 @ Figure 2 Figure 3 Figure 4

Claims (3)

[Claims] (1) Access to the main memory is protected using ring levels and access restrictions, and information on the ring levels and access restrictions is stored in an address translation table, and the ring levels (reference ring levels) and programs held in the address translation table In a computer that controls the restriction conditions of access restriction information by comparison with the ring level (execution ring level) on the status word (PSW), the reference ring level (RL_R) and execution ring level (RL_E) are determined in the mapping mode. ), when RL_E=0, access is allowed without restriction, when RL_E≦RL_R, access is allowed according to the access restriction information, when RL_E>RL_R, only reading is allowed, and in direct mode, execution is possible. Always refer to the ring level (RL_E).
) is provided, and the memory protection method is characterized in that the memory protection is effectively operated both in the mapping mode and in the direct mode. (2) Separately from the access restriction information on the address conversion table, a first memory that has access restriction information for each real page of the main memory, and access restriction information for small unit capacity within the real page. The information in the first memory is used to determine whether or not to restrict access to small units within the real page, and in the direct mode, the contents of the first or second memory are Access is restricted by the access restriction value generated by ANDing the access restriction information on the address translation table and the access restriction information in the first or second memory in the mapping mode. A memory protection method according to claim 1. (3) If an address translation buffer (ATB) is provided to process address translation at high speed, and there is access restriction to the small unit capacity within the page unit, when registering to the ATB, the address of the access small unit capacity is The scope of the claim is characterized in that the numbers are registered at the same time, and when the ATB is referenced, the address number in the reference address and the address number in the ATB entry are compared to execute memory protection processing in small capacity units at high speed. The memory protection method described in Section 2.