JPH0296846A - Logic analyzer - Google Patents

Abstract

PURPOSE:To effectively utilize a logic analyzer by varying the data memory capacity of the logic analyzer by means of the number of use channels. CONSTITUTION:A use channel number setting means 9 sets the number of the channels of digital information which require writing. A selector 10 sequentially writes digital information having the set number of the channels into the memory 5 of the channels which correspond to or which do not correspond to the number of the channels. Thus, the memory capacity can be enlarged when the number of the channels of digital information is small, and the logic analyzer can effectively be utilized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic analyzer that traces and analyzes the operating state of a device to be analyzed, such as a microprocessor f'.

[Conventional technology]

FIG. 2 is a block connection diagram showing a conventional logic analyzer shown in, for example, the electronic magazine "Electronics" Vol. 27, No. 12, pages 1177-1188.
Reference numeral 1 denotes a device to be analyzed, such as a microprocessor whose operation history is traced and analyzed. 2 is a comparator that receives, for example, address information from the analysis target device 1;
Data information.

Control signals, status signals, 5-tHta, etc. are taken in as input data S1. This comparator 2
is the logic level of the input data S1 imported as above,
That is, it is determined whether it is 1" or "0", and for example, address information and data information are sent as logic level input data S2, and control signals, status signals, and error information are sent as logic level control signals S3 to the buffer memory 3 and clock generator 4, respectively. 3 is a buffer memory, which temporarily stores the logic level input data S2 from the comparator 2 and outputs the buffer memory output data S5.
It is output to the data memory 5 and trigger generator 6 as 4 is a clock generator which generates backup memory control signals S4 data memory control signals S6 . A trigger generator control signal S7 as a timing signal is generated, and each backup memory 3. Output to data memory 5 and trigger generator 6. This trigger generator 6 determines the trigger and trace conditions based on buffer memory output data S5 given from the buffer memory 3 and trigger generator control signal S7 given from the clock generator 4, that is, the timing of data output from the data memory 5, or The trigger signal S8 is generated and given to the data memory 5 after making settings and determinations such as under what conditions such data should be selected.

The data memory 5 transfers the buffer memory output data S5 output from the backup memory 3 to the data memory control signal S6.
Accordingly, the stored data is stored in time series according to the trigger signal S8 given from the trigger generator 6 described above as data memory output data S9. 7 is a display generator which converts the data memory output data S9 outputted from the data memory 5 into display data SIO and outputs the same. 8 is a CRT display, which displays the analysis results in accordance with display data S10.

The operation of the conventional logic analyzer configured in this way is as follows.

Input data S1. taken in from the analysis target device 1 to the logic analyzer. In other words, the logic level of address information, data information, control signals, status signals, error information, etc. is determined by the comparator 2 and is set to "1" or O.
is converted into binary digital information.

Address information and data information are supplied from the comparator 2 to the buffer memory 3 as logic level input data S2. Also clock generator 4
A control signal, a status signal, and error information are given to the buffer memory 3 as a logic level control signal S3, and the cyclic generator 4 generates a buffer memory control signal S4 and supplies it to the buffer memory 3. buffer memory 3
is the comparator 2 according to the buffer memory control signal S4.
Logical level input data S is synchronized with the analysis target device 1 from
Capture and store the data from step 2.

The data stored in the backup memory 3 is sequentially transferred to the data memory 5 and stored therein in accordance with the data memory control signal S6 given to the data memory 5 from the stock sigma generator 4.

This storage in the data memory 5 will be explained with reference to Figure 8g3. FIG. 3 shows a four-channel logic analyzer as an example. According to this, the memory capacity is determined for one channel! - (in this case, IK bits) memory is fixedly used, and when this memory with IK bit capacity becomes full, data is stored again from the first memory address of this memory. Then, writing to the memory is inhibited by a signal from the trigger generator 6, and the data is displayed on the CRT display 8 through the display generator 7.

[Problem to be solved by the invention]

Since the conventional logic analyzer is configured as described above, since the capacity of the data memory 5 per channel is fixed, it is impossible to analyze data exceeding that capacity. However, there are problems in that the data memory 5 of unused channels may not be used effectively.

This invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a logic analyzer that can effectively use the data memory by making the capacity of the data memory variable depending on the number of channels used. .

[Failure to solve the problem]

In the logic analyzer according to the present invention, the number of channels of digital information that needs to be written is set by the number of channels to be used setting means, and the digital information of the set number of channels is set by the selector to correspond to and correspond to the number of channels. In this configuration, data is sequentially written to the memory of the channels that are not used.

[Effect]

The selector of the present invention is designed to sequentially write the digital information of a set specific channel into the memory on the data memory of the channel corresponding to this specific channel, as well as into the memory of a channel that does not correspond to the specific channel. This makes it possible to expand the memory capacity when the number of digital information channels is small.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 2 is a comparator that converts the logic level of data taken in from the device to be analyzed and outputs it as digital information, 3 is a buffer memory that temporarily stores the digital information, and 5 is a per-channel unit that stores digital information.
91 is a data memory with bit memory (here, 4 channels), S9 is the output data of data memory 5,
I is a display generator for generating the output data S9 and outputting it to the display device, 6 is the trigger generator explained in the prior art, 4 is a clock generator that controls writing to the data memory 5, and 9 is a setting for the number of channels used. A switch 10 for setting the number of channels to be used is a selector for selecting one channel of digital information from four channels of digital information.

Further, 11 to 14 are logics that output a write control signal for each channel of the data memory 5 together with the four selectors 10, and 15 is a logic that outputs a selector operation signal to the logics 11 to 14 in response to a detection signal from the data memory. This is a logic control circuit that outputs.

Next, the operation will be explained. First, the number of channels to be used for digital information is set using the switch 9 for setting the number of channels to be used. This number of channels is when switches St and So are on,
By selecting the off state, settings are made as shown in Table 1.

Table 1 Here, for example, turn off the number of channels used, S.

Turn on So to set channel 1.

Then, the selector 10 selects all the digital information to be sent to the data memory 5 on the data line of one channel. Further, a write control signal C8 to the data memory 5 that permits writing to the data memory 5 is sent to IK from each selector 10 and logic 11 to UK as shown in Table 2.
Each bit is selected sequentially.

Therefore, once the IK bits of digital information for one channel are written, that memory is held as is, and the next portion of the digital information begins to be written into the memory of the next channel. In this way, when one channel is used, digital information at bit t can be stored one after another in 4 bits.

In the above embodiment, a four-channel logic analyzer has been described, but the same effect can be obtained with a logic analyzer having a larger number of channels using the same circuit type.

Further, in the above embodiment, the channel number setting switch 9 is used as the channel number setting means, but other setting devices or setting parts may be used.

〔Effect of the invention〕

As described above, according to the present invention, the data memory capacity of the logic analyzer is configured to be variable (depending on the number of channels used), so a multi-channel, small-capacity logic analyzer can be changed to a small-channel, multi-capacity logic analyzer. In addition to making effective use of the logic analyzer, it is possible to use the logic analyzer effectively, and depending on the application, it is possible to use two logic analyzers instead of the conventional one.
This has the advantage that a single logic analyzer can store a large amount of digital information.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a logic analyzer according to an embodiment of the present invention, FIG. 2 is a block connection diagram showing a conventional logic analyzer, and FIG. 3 is a block connection diagram showing details of data memory in a conventional logic analyzer. It is a diagram. 1 is a device to be analyzed, 2 is a comparator, 9 is a means for setting the number of used channels (number of used channels setting switch), 1
0 is a selector. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation. Agent Patent attorney 1) Hiroshi Sawa (2 others) [1

Claims (1)

[Claims] A comparator that converts the logic level of the data taken in from the device to be analyzed and outputs it as digital information, and a data memory that stores the digital information of multiple channels output by this comparator and has memory corresponding to each of these channels. In a logic analyzer equipped with a logic analyzer, a number of channels to be used setting means for setting the number of channels of the digital information that requires writing;
A logic analyzer comprising a selector for sequentially writing digital information of the set number of channels into the memory of channels corresponding to and not corresponding to the set number of channels.