JPS61235956A - Event recording system - Google Patents

Abstract

PURPOSE:To facilitate operation analysis of a faulty device by selecting a specific device to apply event recording and applying event recording in a timing proper to a recorded event. CONSTITUTION:When a channel for event recording is designated from a service processor 13 or a microprocessor 20, an event applying event recording is selected by the low-order 4-bit of a control word in a register 3 and the result is outputted via a signal line 17. On the other hand, a trigger generating condition is selected by the high-order 2-bit of the control word in the register 3 and the circuit 12 generates a trigger signal and outputs it in the corresponding timing. A register 15 corresponding to the channel is made enable by using a trigger signal and a channel selection signal obtained by encoding the value of a register 21 and after the signal of the event sent via the signal line 17 is latched to the register 15, the result is stored in an event recording area of a storage device 19 via the signal line 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a system for recording events of a device related to input/output control of a computer.

[Background of the invention]

Conventionally, event recording systems for normal operation or abnormal operation of a device are known.

For example, Japanese Patent Laid-Open No. 58-112147 discloses a technique related to this field. However, when multiple devices share one event recording area of a host device,
There is no known method of extracting only a device in which an abnormality has been detected or a specific device and recording the event.

[Purpose of the invention]

A fourth object of the present invention is to select a specific device when multiple devices share one event recording area of a host device;
Moreover, it is an object of the present invention to provide an event recording method that records an event at a timing suitable for the event to be recorded.

[Summary of the invention]

The present invention provides a means for specifying a lower-level device that performs event recording, a means for capturing an event signal sent from the specified lower-level device based on a trigger signal sent from the lower-level device, and a common device for storing the event signal. a host device having a storage device, a means for specifying an event to be recorded, a means for specifying a timing for collecting an event, and a means for selectively transmitting only a signal of the specified event. The present invention is characterized by an event recording method comprising: a lower device having a means for transmitting a trigger signal that provides a timing for capturing an event based on the timing designation;

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows a channel controller (CHC) 1, a channel (CH) 2 below it, and an input/output device below it (CHC) 1.
It is a block diagram showing a configuration consisting of I/(15)ao, particularly the configuration within channel 2. A control memory (C8) 4 is a control memory device that controls the entire channel 2, and a register 14 is an address (C8) of this control memory 4.
HAR) and data buffer 8 are I/T
This is a buffer that temporarily stores data exchanged between 5so and Chaol 2. The signal line 9 is a signal line through which a bus out signal (output data signal) is output to the Φ30.
Signal line 10 is I/? ) 30 to which a bus-in signal (input data signal) is input. Register 6 is a register that latches an out tag signal (output control signal), and register 7 is a register that latches an in tag signal (input control signal). The signal line 23 is a signal line to which an out tag signal is output to I/(53o, and the signal line 24 is l10
This is a signal line to which an intag signal is input from 30. Register 5 is a register used to control channel 2 in addition to the above. The above-mentioned components are mechanisms that are normally included in the channel 2.

The mechanisms added for the purpose of the present invention in FIG. 1 are a register 3, a circuit 12, and a selector 11. The register 3 is a register for providing information (called a control word) for controlling the event recording of the present invention, and is set by the 8VP 13 through the control signal line 31.

In this example, the control word is given as 6 bits, and the lower 4 bits specify two events to be recorded by a combination of these 4 bits. Table 1 shows the events corresponding to each of these 4-bit combinations. For example, the combination (1ooi)2 specifies that the contents of register 6 and register 5 are to be recorded. The upper two bits of the control word specify the timing conditions for event recording. Table 2 shows the timing conditions for each of these two-bit combinations.

Table 1 Table 2 "Machine cycle synchronization" indicates that event recording is performed in synchronization with the machine cycle of channel 2.

"When tag changes" is mainly channel 2 and I/? )a.

It is used for the signal line of the I10 interface between the register and indicates that event recording is performed only when the contents of the register change. For example, register 14 (C8A
Register 5 (9EG), etc. are updated in synchronization with the machine cycle of channel 2, so to record these events, write (00)2 or (11)2 as the upper two bits of the control word. All you have to do is select. On the other hand, signal ll15
Since the signals on 19, 10, 23, and 24 change at a time several tens to hundreds of times longer than the machine cycle of channel 2, in order to record events related to these signal lines, as bits (10) or (01)2
If you select , the amount of storage space required to keep event records will be small, and it will be efficient.

Note that in the case of (01)2, when CH2 is a block multiplexer channel, tracing is performed "at the time of tag change" during data transfer, and in all other cases, tracing is performed in synchronization with the machine cycle.

Circuit 12 is a circuit that decodes the upper two bits of the control word in register 3, inputs the machine cycle of channel 2 and the contents of registers 6 and 7, and generates a trigger signal that provides the timing for event recording. be.

The signal line 16 is a signal line that supplies a trigger signal generated by the circuit 12 to the channel controller 1. Selector 11
is a selector that selects the signals of two event sources from each event source using the lower four bits of the control word in register 3. Signal line 17 is a signal line that sends signals of two selected events to the other channel controller.

FIG. 2 is a block diagram showing the internal structure of the channel controller 1. As shown in FIG. The microprocessor 20 is a processor that controls the entire channel controller 1. Register 21 is a register in which a channel for event recording is designated, and holds 3-bit information. The encoder 33 is a circuit that encodes this information. The encoded value of these 3 bits corresponds to channels from channel number O to channel number 7. The service processor 13 is connected to the channel controller 1 and is a diagnostic device that diagnoses the channel system. Channel designation of the register 21 can be performed manually from the service processor 13 or can be performed from the microprocessor 20. The OR circuit 22 is an OR circuit that allows channel designation from either the service processor 13 or the microprocessor 20. There are eight registers 15 corresponding to the encoded values output from the encoder 33, and they are enabled by a trigger signal sent from the signal line 32 and signal line 16 for selecting the channel obtained by encoding the value of the register 21. , latches the event signal sent via signal line 17. The storage device 19 is a storage device in which the contents of the register 15 are stored via the signal line 18.

The operation of this embodiment will be explained below. When a channel for event recording is specified by the service processor 13 or microprocessor 20, the register 21 is set so that the encoded value selects the corresponding channel. Further, a control word is set in the register 3 from the service processor 13 via the signal line 31. register 3
An event to be recorded is selected by the lower four bits of the control word in the control word, and the selector 11 selects the signals of the two corresponding events and outputs them via the signal line 17.

On the other hand, the trigger generation condition is selected by the upper two bits of the control word in the register 3, a trigger signal is generated at the corresponding timing by one circuit 12, and the signal is transmitted to the signal line 1.
6. The register 15 corresponding to the channel is enabled by the channel selection signal obtained by encoding the value of the register 21 and sent via the signal line 32 and the trigger signal sent via the signal line 16. After the event signal sent via the signal line 17 is latched into the register 15, it is stored in the event recording area of the storage device 19 via the signal line 18. This event recording area is finally recorded in a wrap-around manner and has a recording area necessary and sufficient for failure investigation.

As described above, according to this embodiment, when a fault occurs in a channel, by checking the register for selecting a channel to record an event and the event recording data of the faulty channel, the number of the faulty channel and the fault are detected. It is possible to know the operation of the channel before and after the occurrence of the occurrence, which can be used to analyze the failure. Since the well-recorded data consists of pairs of data that are closely related to each other, such as the out tag signal and the bus out signal, it is easy to analyze failures.

〔Effect of the invention〕

According to the present invention, it is possible to select a specific device and record an event, and to record the event at a timing appropriate for the event to be recorded, thereby providing an efficient event recording method that facilitates operation analysis of a faulty device. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a channel according to an embodiment of the present invention, and FIG. 2 is a block diagram of a higher level device of the channel according to an embodiment. 1...Channel controller 2...Channel 3...Register 11...
・Selector 12...Circuit 19...Storage device 21...Register cold diagram

Claims (1)

[Claims] In an event recording method in which events of multiple lower-level devices related to input/output control are recorded in a common storage device of the higher-level device, there is a means for specifying the lower-level device to record the event and a trigger signal sent from the lower-level device. a higher-level device having means for capturing an event signal sent from the designated lower-level device, and a common storage device for storing the event signal;
A means for specifying an event to be recorded, a means for specifying a timing for collecting an event, a means for selectively transmitting only a signal of the specified event, and a means for specifying a timing for capturing an event based on the timing specification. and a lower device having means for sending out a trigger signal.