SU769524A1 - Information input arrangement - Google Patents

Description

The invention relates to the field of computer technology and can be used in interface devices for electronic computers with non-standard sources of information for inputting large amounts of experimental data into computers. The proposed device can be used in automated processing systems for inputting into the computer large arrays of experimental data that have a recording frame structure in multi-channel measurements. Devices for inputting information into computers are used, which are used in the composition of a complex of technical means of various systems of automated processing of experimental data. A device for processing and inputting experimental data into computing machines jl} is known, comprising a matching and switching unit, a time shift compensation unit, a channel selection unit, a time code allocating unit, a data rarefaction unit, a control unit, a code conversion unit, a computer word generating unit, an interface with a computer. A disadvantage of this device is that it cannot function if it is necessary to select channels from information frames of variable length and structure containing a large number of channels (up to hundreds of thousands of hours). A close technical solution is an information input device 23 / comprising a playback unit, a generation unit, a comparison unit, a channel counter, an information selection unit and a control unit. The disadvantage of this device is that it cannot function in the processing of experimental data, when entering arrays of information from non-standard sources, which contain a variable number of information channels (from several tens to hundreds of thousands of hours), into the computer, due to the limited possibilities in the analysis and selection of information channels, the data from which are to be entered into the computer. The aim of the invention is to expand the field of application of the device. This goal is achieved by the fact that the device for inputting information contains blocks for generating, comparing, selecting information, control, and a playback unit, whose input is the first input of the device, and the first and second outputs of the reproducing unit are connected through an information selector and a comparison unit. the first and second inputs of the control unit, the output of which is connected to the first input of the formation unit, the third output of the playback unit is connected to the second input of the formation unit, the output of which is a device output, a memory block and a channel selection block are entered, the first and second outputs of which are connected respectively to the first and second inputs of the memory block, and the third output is connected to the third input of the control unit, the first input of the channel selection block is connected to the fourth output of the block playback, and the second with the output of the memory unit, the third input of which is the second input of the device. The device channel selection block contains an AND element, the first input of which is connected to the input of the delay element and is the first input of the block; The delay of the delay element is connected to the control inputs of the bit counter, the shift register and the trigger, the output of which is the third output of the block; the second input element And is connected to the output of the first decoder, the input of which is connected to the first output of the bit counter, the second output of the bit counter is connected to the input of the second decoder, the output of which is connected to the second input of the bit / rand counter and the control input of the address counter, the output of the address counter is the second output of the block, the first output of which is connected to the output of the element I, the second input of the block to the second input of the shift register, the output of which is connected to the second input of the trigger.

The drawing shows the block scheme of the device in question, which comprises a playback unit 1, a generation unit 2, a comparison unit 3, an information selection unit 4, a control unit 5, a memory unit 6 and a channel selection unit 7.

The channel selection block contains an AND element 8, a shift register 9, an address counter 10, a bit counter 11, a first decoder 12 ,. the second decoder 13, the trigger 14 and the delay element 15, the inputs 16, 17 and output 18.

The device operates as follows. Measuring information from a magnetic tape through the playback unit 1 in the form of a certain periodic sequence of codes, the totality of which constitutes an information frame, enters the block 2 of the formation of a computer word.

and service information (tracking pulses, markers, etc.) in the channel selection section 7, permission to enter information from a given channel into the computer comes from the output of this block to the control unit 5. From the output of the computer word formation unit, the information goes to the computer through the output of the device 18.

Comparison unit 3 and information selection unit 4 are used for sampling information when entering into a computer according to specified initial conditions (a time code and the number of information frames entered in a computer recorded on a magnetic tape). At that, the permission to output information to the computer comes from these blocks to the control unit 5.

The channel selection unit 7 operates as follows; Before starting operation, overhead information is loaded into the memory unit 6 from the device 17 input, which contains the position code of the channels, the data from which are to be entered into the computer. The current channel number is associated with memory block 6 as follows:

Ni k-p + Ni current number

where the channel of the information frame is the sequence number of the memory cell; number of bits

n - memory block cells;

{o, 1,2. . .n-i is the shift register bit number (position of the i-th channel in the memory location at the W-th address).

The address of the i-th channel in memory block 6 is uniquely determined as a whole part of the ratio,.

The presence of a unit in a given memory location indicates that the information of the corresponding channel is allowed for input into a computer.

When playing information, the impulse of tracking the first channel from the output of block 1 is fed to the input of the element And 8, to the other input of which the resolution comes from the first decoder of zeros 12, because at the initial moment the bit counter 11 contains a zero code. The address counter 10 also contains a zero code.

Claims (2)

From the output of the element 8, the tracking pulse arrives at the control input of the memory block 6 and the information at the zero address is read into the shift register 9. The tracking pulse detained on the delay element 15 adds one to the counter 11 and simultaneously shifts the register code 9 to the right. that the zero () bit of the code corresponding to the first channel number enters the trigger 14 whose output through the control unit 5 controls the resolution of the input of the first channel information into the computer. The tracking impulse of the second channel does not pass to the control input of the memory block b, since the counter 11 contains a non-zero code and the output from the decoder 12 element does not receive a permission for the input of the element 8. The delayed tracking impulse of the second channel adds one to the counter bits 11 and shifts the register code 9 to the right. Thus, the first (E 1) code bit corresponding to the second channel falls into trigger 14. Then the cycle repeats with the arrival of 3, 4, 5, n-1, channel tracking pulses. In the course of the pth pulse, the last nth digit of the code E (n - 1) is outputted from register 9 to trigger 14, and at the same time one is added to the bit's counter 11. At the same time, a code is generated in the counter of bits 11 The counter state is decrypted by the decoder of bits 13, which, with a signal from its output, resets the counter of bits 11 and thereby prepares the resolution at the second input of the element 8 At the same time, the signal from the output of the decoder of bits 13 increases by one the address of the memory block 6 by adding one to the count IR address 10, and a passing (n + 1) -th tracking pulse (n + 1) -th channel reads from the 6pam block of the position code of the next group of channels into the shift register 9. The process described below is repeated. The frame start flag (marker) sets the counters 10 and 11 to the zero state. The efficiency of using the proposed device for calculators is increased when inputting measurement information into a computer from multichannel magnetic code drives — information sources due to computer processor unloading from unproductive sorting operations and selection of experimental data. Claim 1. A device for inputting information containing playback units, formating, comparing, selecting information and controlling, wherein the input of the playback unit is the first input of the device, and the first and second outputs of the playback unit are connected via the information selection unit and the comparison unit respectively. and the second inputs of the control unit, the output of which is connected to the first input of the formation unit, the third output of the playback unit is connected to the second input of the formation unit, the output of which is The device output, characterized in that, in order to expand the field of application by processing data from non-standard information sources, a memory block and a channel selection block are entered into the device, the first and second outputs of which are connected to the first and second memory blocks, respectively the third output is connected to the third input of the control unit, the first input of the channel selection unit is connected to a quarter output of the playback unit, and the second to the output of the memory unit, the third input of which is the second input of the device, 2. Device The device according to A.1, which means that the channel selection block contains an AND element, the first input of which is connected to the input of the delay element and is the first input of the block and the code of the secondary element is connected to the control inputs of the bit counter, the shift register and a trigger whose output is the third output of the block; The second input of the element I is connected to the output of the first double-digger, the input of which is connected to the first output of the bit counter, the second output of the bit counter is connected to the input of the second decoder, the output of which is connected to the second input of the bit counter and is controlled (Ш (IM address address counter, the output of the address counter is the second output of the block, the first output of which is connected to the output of the AND element, and the second input of the block is connected to the second input of the shift register, the output of which is connected to the second input of the trigger. into account in the examination 1. The author's certificate of the USSR 520581, CL G 06 F 3/04, 1976. 2. USSR author's certificate number 447710, cl. G About F 3/04, 1974 (prototype).