SU1564606A1 - Multichannel device for input/output of analog information - Google Patents

Abstract

The invention relates to automation, computing and can be used in information-measuring complexes, data acquisition systems and other devices of similar purpose for communication with linear and functional sensors and receivers of analog signals. The aim of the invention is to simplify the device. The goal is achieved by introducing into the device an arithmetic logic unit, a register, a hardware multiplier, and a non-standard inclusion of a digital-analog converter. The new structure makes it possible to combine in the arithmetic logic unit the functions of conversion and the sequential approximation register for analog-digital conversion, together with the multiplier, the functions of functional transformation and the functions of the PDD controller in exchange with the system memory. 4 il.

Description

The invention relates to automation and computational techniques and can be used in information collection systems for receiving signals from analog information sensors and for issuing analog signals as relative voltage values.

The purpose of the invention is to simplify the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 is a diagram of an interface unit, an example of execution; in fig. 3 is a diagram of the first switch, an example of execution; in fig. 4 - the algorithm of the device.

The device contains (Fig. 1) first to fourth switches 1-4, an inverter 5, a memory block 6, a digital-to-analog converter (D / A converter) 7, an amplifier. 8, the comparator 9, the conjugation block 10, the control block 11, the arithmetic logic unit 12, the register 13 and the multiplier 14. FIG. 1 also denotes an input 15 of the reference voltage of the device and elements 16 and 17 of the D / A converter 7.

A DAC 7 can be implemented on an LSI 572 Series DAC. In this case, the first DAC input is the LSI feedback input, the second DAC input is the input of the LSI reference voltage, and the DAC group inputs are BIS digital inputs.

Unit 10 (FIG. 2) can be implemented on an LSI 588VP protocol controller and an LSI transceiver 588BA1, unit 11 - to a LSI 538VU2, unit 12 - to a LSI 583BC2, multiplier 14 - to BIS 533BP1 in the standard power-on,

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The device works as follows.

The operation of the device is carried out under the control of the firmware control unit 11, which implements the algorithm of operation of the device, a block diagram of which is shown in FIG. four.

The micro-command size, formed by block 11, is determined by the block, 12 and is 12 bits for 588BC2, and the micro-command block of the control block 11 is 5 bits for 588BG1, which is part of the size of the microcommand. The remaining free bits of the microcommand are connected to the data inputs of the register 13, the outputs of which are internal device control signals. The block 11 generates two signals of the microcommand tracking (strobe): the first arriving at block 12 and the second arriving at the control input of block 10 and the control input of the register 13, which record the microcommand into the corresponding registers of these blocks, therefore the signals at the output of the register 13 can change only when referring to block 10, i.e. by microinstructions followed by a strobe at the output of the control of block 11. In microcommands of access to block 12 and to block 10, block 11 performs the transition to the next microcommand, and the microprogram branch occurs according to the result of analyzing the signals input to the signs of block 11, such signs are the outputs of the signs of unit 12 and the output of the comparator 9.

The implementation of the analog-digital and digital-analog conversion task involves the sequential execution of the following processes:

1.linear transformation knew

signals into digital code; digital functional code conversion (for a functional channel); recording the result of the conversion into the system memory;

2, read data from the system

Charger for conversion to analog signals

digital data conversion (for a functional channel), linear digital-to-analog conversion.

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Thus, linear analog conversion, functional digital conversion, and data exchange with the system memory in direct access mode proceed sequentially in the device.

In analog-to-digital conversion, the signal from the first output of the register 13 connects through switch 2 and switch 1 the signals of the selected channel to the inputs of switch 3. Data from the information outputs of block 12 is fed to the control inputs of switch 3 and the DAC 7. The analog-digital conversion is performed by the serial method balancing. In this case, the function of the sequential approximation register is performed by block 12, which controls, through the outputs, the conductivity of the CAP 7.

The signal 0-mismatch amplifier through the comparator 9 is fed to the input of the characteristics of the block 11 and provides control (branching) of the executed conversion firmware.

The higher bits of the information outputs of block 12 function as control lines of switch 3. In the first two conversion cycles, the signs of both input signals are sequentially determined (which corresponds to sine and cosine signs for the angular parameter). To do this, the input of the amplifier 8 through DAL 7 (element 16 of a single conductivity) switch 3 under the control of the unit 12 connects in series the first and second lines of the input analog signal. The conductivity of the DAC element 17, defined by the code at the inputs of the DAC 7 group, is set to zero. In this case, the signs of the input voltages are determined by the output state of the comparator 9,

Then, the mutual ratio of the signal values in the input channel lines is determined. To this end, the signals, taking into account the signs defined previously, are connected to the input of the amplifier 8 through the elements 16 and 17, the conductivity of the element 17 is set equal to one. In the case of equal signs of voltages on the lines, the signal to the input of element 16 is connected via an analog inverter 5. The ratio of the magnitudes of the signals is determined by the output state of the comparator 9.

Thus, three senior (sign) code bits are defined. Taking into account

51564606

Signs and signal level ratios are connected to the input lines to the amplifier 8 so that the lower level is connected via element 16, and the larger one is through the DAC element 17 of the DAC 7.

Then, the code bits corresponding to the conductivity of the element 17 1/2, 1/4, 1/3, and so on, are sequentially installed on the information outputs 0 of block 12. According to the state of the comparator 9, taking into account the three most significant bits of the code, the corresponding code bit is either left or removed. Thus, the conversion result corresponding to the linear ratio of the input voltages is formed in block 12, the control element 17. For the input linear parameters representing the voltage ratio, this result is final, an additional transformation is required for the functional parameters. Thus, for the input angular parameter transmitted in the form of a voltage proportional to the sine and cosine of the angle, the result of the X sinA / cosA TanA transform, which obviously requires the calculation of the arc tangent function of the argument.

When digital-to-analog conversion, the signal from the first output of the register 13 switches the switch 2 to the decoding mode, while the input voltage of the amplifier 17 through the element 17 receives the reference voltage from the input 15, and through the element 16 - the error signal from the output of the amplifier 8. At the same time communication on the error signal at the output of the amplifier 8 sets the voltage UBUX ucn X, where uon is the reference voltage at the input 15; X is the conductivity of element 17 defined by the code at the control inputs of the DAC 7.

To control the sign of the output voltage, the reference voltage to the input of the element 17 can be supplied via an analog inverter 5. Switches 3 and 4 are controlled by control inputs connected to the information outputs of the higher bits of the block 12. The signal from the second register output 13 allows recording into the selected channel of the multichannel block 6 of the memory of the converted signal and the reference voltage for their storage.

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For functional output channel information | The received from the system memory is subjected to digital functional transformation before performing linear digital-to-analog conversion. Thus, for angular parameters, the code for angle A, read from memory, is converted to TapA and, after a linear transformation, the voltage uon is formed on one of the lines. a on the other, voltage, and, tapa.

Functional digital conversion is performed by calculating a function through a power series. To increase accuracy and reduce computation time, a multiplier 14 is introduced into the device. The operation of the multiplier is controlled by register 13, the third, fourth, and fifth outputs of which are connected to the write, read, and multiplier addresses.

The data obtained as a result of the conversion of the analog value of the selected input channel is recorded in the system memory, and the data read from the memory and converted to the analog value is transferred to the analog receivers through the memory block L.

Oo -, en data with the computing system is made in the mode of direct access to the system memory, which eliminates the need for software service exchange with the device.

Claims (1)

For this, in block 12, the system addresses of the input and output parameters are formed and modified with each access to the memory. In the input cycle, the system address is transmitted through the information outputs and transceiver of unit 10 to the system bus, and data from the memory device arriving via the system bus is entered into unit 12 via the transceiver and used for subsequent conversion. In the output cycle, the address is transmitted as described, and the result conversion is transmitted via the transceiver to the system bus. Synchronization of the exchange over the system bus by issuing from the block 12 addresses of the exchange and receiving (issuing) data from block 12 is carried out by the block 10, controlled by the block 11. The exchange interface over the system bus corresponds to the PIM 26765.51-36. Invention Formula Multichannel device for input-output analog information, co0 five 0 five five holding control unit, memory unit, interface unit, four switches, digital-analog converter amplifier, comparator, inverter, inputs of the first switch are the analog inputs of the device, outputs of the First switch are connected to the first and second inputs of the second switch, the first and The second outputs of which are connected respectively to the first and second inputs of the third and fourth switches, the first output of the second switch is connected via an inverter by 4 third inputs of the third and fourth switches, the outputs A ground switch is connected to the information inputs of a memory unit whose outputs are analog outputs of the device, the first output of the third switch is connected to the first input of a D / A converter, the output of which is connected to the input of the amplifier, the output of which is connected to the input of the comparator and the third input of the second switch, the fourth input of which is the input of the reference voltage of the device, the first group of inputs-outputs of the interface block is the information inputs-outputs of the device, the second groups and the inputs / outputs of the interface block are device control inputs-outputs, characterized in that, in order to simplify the device, 0 5 0 five it contains arithmetic logic unit, multiplier, register, outputs of microcommands of control unit connected to information inputs of arithmetic logic unit, group of outputs of control unit connected to control inputs of arithmetic logic unit, group of control input inputs of the interface unit and information inputs of the register, output the control unit is connected to the control inputs of the register and the interface unit, the outputs of the attributes of the arithmetic logic unit and the output of the comparator are connected to the inputs of the characteristics of the control unit , The information inputs-outputs of the arithmetic logic unit are connected to the information inputs-outputs of the interface unit and multiplier, to the control inputs of the third and fourth switches and to the inputs of the information converter group, the first output of the register is connected to the control input of the second switch, the second and third outputs the register is connected respectively to the write and read inputs of the multiplier, the outputs of the first register group are connected to the address inputs of the memory unit, the outputs of the second register group are connected to the address bubbled inputs of the multiplier, the second output of the third switch is connected to the second input of the DAC. Phage.1 1 gpf g # JOHft / P UJJflJ but 909V9SI From the beginning) Formation of initial addresses Reading data for decoding Not Decoding Not Coding result records Formation of the following address address Not 12  Of course. Yes dresa J5K array