SU862366A1 - Digital corrector of signals - Google Patents

Description

(54) DIGITAL SIGNAL CORRECTOR

one

The invention relates to telecommunications and can be used to correct intersymbol interference in modulated signals.

A digital signal corrector is known, which contains an analog-to-digital converter, the outputs of which are connected to the first inputs of the memory unit and the program block, the first output of the latter being connected to the second input of the memory block, first, to the inputs of the coefficient memory block and the arithmetic unit whose output is the output of the device, and the second input is through the memory block of coefficients pdc connected to the output of the correlation block, the second output of the memory block is connected to the third input of the arithmetic unit, the second output of which is connected the third input of the storage unit 1 minute.

However, in a known device, the presence of a constant component in the signal at the output of the equalizer significantly reduces the noise immunity of the transmission.

The purpose of the invention is to improve noise immunity.

For this, a known digital signal equalizer containing an analog-digital converter, the outputs of which are connected to the first inputs of the memory block and the program block, the first output of the last one is connected to the second input of the memory block, the first inputs of the coefficient memory block and the arithmetic block whose output is the output of the device, and the second input through the coefficient memory block is connected to the output of the correlation block, the second output of the memory block is connected to the third input of the arithmetic block, the second output of which is connected A control unit is inserted at the third input of the memory unit. In this case, the outputs of the control unit are connected to the control inputs of the memory unit, the correlation unit, and the program unit, respectively. The first output of the latter is connected to the third input of the correlation unit, and the second output is connected to the input of the control unit.

The drawing shows a structural electrical circuit of the proposed device.

20

The digital signal equalizer comprises receiver 1, digital equalizer 2, analog-digital converter 3, memory block 4, program block 5, correlation block 6, coefficient coefficient block 7, arithmetic block 8, and control block 9.

The device works as follows.

The analog signals from the outputs of the demodulators of the receiver 1 are fed to the analog-to-digital converter 3, where they are gated at the reference times, storing and storing the amplitudes of the received sample voltages and converting these voltages into n-digit code numbers.

The conversion is performed in such a way that the signal from the output of the first demodulator oi is first converted, and then the signal from the output of the second demodulator L / receiver 1. In the same order, two memories of two n-bit numbers of samples received in result of conversion. The same block from the output of the arithmetic unit 8 records the polarity of the signals aj and aj at the outputs of the digital equalizer 2 (Sgna -, Sgna) / and the signals Sgnlj and Sgnl, displaying the sign from the deviation of the corrected signals aJ and a from the normalized value.

Based on the analysis of these signals outputted from memory block 4 by the commands of program block 5, and in accordance with the selected algorithm of the digital corrector 2 in correlation block 6, signals about the direction of change of the transfer coefficient of the corresponding tap of the corrector 2 are generated, which in the form of bit numbers are stored in the coefficient memory block 7. In each cycle of operation of software block 5 from blocks 4 and 7, two multiplication code numbers are sent to the multiplication unit of arithmetic unit 8, corresponding to the modules and fields of the transfer and sampling codes for the corresponding offset of the equalizer 2.

Here, first, in the arithmetic unit 8, nocTiyn aeT, the sample code of the first demodulator aj, and then the sample code of the second demodulator a / receiver 1 for multiplying by the same controller gain code. The resulting products of two pairs of numbers are written by commands from program block 5 to one of the two adders of the arithmetic unit 8 in order to add the products separately for the signal samples from the outputs of two demodulators.

In the next cycle of operation of software block 5 from blocks 4 and 7, code numbers corresponding to the next tap of corrector 2 will be fed to the inputs of block 8. The resulting products are algebraically added in the corresponding adders of block 8 with numbers stored in

it from the previous cycle of operation of block 5 for the prior tap of corrector 2. This process will continue until the sums obtained as a result of

addition of products of sample codes and transmission coefficients for all taps of the corrector 2.

In the process of adjusting offset 2, in block 7, such numbers of transmission coefficients for tap controllers are recorded at which the intersymbol interval is minimal.

Thus, by introducing a control unit into a digital equalizer, the constant component in the signals is compensated, which increases the noise immunity of data signal transmission.

Claims (1)

Invention Formula A digital signal equalizer containing an analog-to-digital converter, the outputs of which are connected to the first inputs of the memory unit and the program unit, 0, the first output of the latter is connected to the second input of the memory unit, the first input of the coefficient memory unit and the arithmetic unit whose output is the device output, and the second input through the coefficient memory unit is connected to the output of the correlation unit, the second output of the memory unit is connected with the third input of the arithmetic unit, the second output of which is connected to the third input of the memory unit, in order to increase 0 noise immunity, a control unit is inserted, the outputs of the control unit are connected to the control inputs of the memory unit, the correlation unit and the program unit, respectively, the first output of the latter is connected to the third input of the correlation unit, and the second output is connected to the input of the control unit. Sources of information taken into account in the examination 1. US patent No. 3633105, cl. 325-42. 1970 (prototype).