SU1231615A1 - Device for compensating intersymbol interference of multilevel signals in data transmission channels - Google Patents

Abstract

The invention relates to telecommunications and provides improved accuracy of the correction of inter-symbol interference. The compare unit (BC) 2 compares the multilevel input and reference signals, which are received respectively from the ADC 1 and the multilevel reference block (L C

Description

Signals- (BFMOS) 7, BS 2 is designed as tn-times of adders, connected 1X sequentially. After each shift of the input signal samples in BS 2, two conversion cycles are performed. In the first cycle, the code bits from the central (n-bit totalizer are copied to the preliminary decision storage unit 3. In the second cycle, the final decision is made signal, the preliminary decision on which is stored

The invention relates to telecommunications and can be used to correct intersymbol interference and received data signals.

The purpose of the invention is to improve the accuracy of intersymbol interference correction.

Pa figs. Figure 1 shows the structural electrical circuit of the intersymbol interference compensation device for multi-level signals in data transmission channels; in fig. 2 is a structural electrical circuit for comparing multilevel input and selection signals; in fig. 3 - structure of the electrical block diagram of the formation of multi-level reference signals.

The compensation device for inter-element interference of multi-level signals in data transmission channels contains an analog-to-digital converter 1, a unit 2 for comparing multi-level input and reference signals, a preliminary decision storage unit 3, a preliminary decision correction unit 4, the first 5 and second 6 decision blocks, block 7 of forming multilevel reference signals.

BLN 2 comparisons of multilevel junction and reference signals consist of g-bit two-input adders 8.

The multilevel reference signal generation unit 7 contains the impulse response sample calculation unit 9, weight modification unit 10, vy31615

in block 4 correction preliminary decisions. For this, the first solver unit (PB) 5 analyzes the signal arriving at BS 2. If the preliminary decision is wrong, then a signal corresponding to the sum of the noise and error samples is received at .РБ 5. In this case, from the RB 5, the BFMOS 7 and the block 4 of the correction of the preliminary decisions receive the corresponding signals. The weight control of the code in BFMOS 7 is carried out using signals from the second RB 6. 2 Cp. f-ly, 3 ill.

borak pulse response and switching unit 11.

The device for compensation of intersymbol interference of multi-level signals in data transmission channels works as follows.

The device realizes the maximum likelihood criterion and minimizes the peak error.

2 | -.t |

i

 I

In accordance with the criterion

max

but

 KUS- K;

where ZJiTj is the sample received

signal;

hjj - counts of the channel impulse response;

d is the number of elementary pulses taken into account in the analysis;

COM is a probability density function;

 - code symbol with sequence number K, corresponding to the i-th position. Sampling of the received signal from the output of the analog-digital conversion312

The body 1 in the parallel m-element code is fed to the first inputs of the t-bit two-input adder 8 of block 2. After each sample shift in block 2, two conversion cycles are performed.

In the first cycle, the n bits of the central t-bit two-input adder 8 are rewritten into block 3. Depending on the sample sign, the outputs of the central t-bit two-input adder 8 in block 2 carry out the algebraic summation of the impulse response samples h; and samples of the signal to be converted. If the signal at the output of the decision block 5 is formed correctly, then in the central t-bit, the two-input adder 8 will remain:

D Po- | -C Z1 h; a

i: -d

 Ki j

where Pr is the noise component of the input signal.

In order to reduce the number of operations of addition (subtraction) of a sample of the impulse response h; algebraically summed with samples stored in n1-bit two-input adders 8 with weights of the signals fixed in block 3. The code weight is controlled in block 11 by the signals received from block 6

In the second cycle, a final decision is made on the value of the transmitted signal, a preliminary decision on which is stored in block 4. By this decisive block 6, the signal at the outputs of the last t-bit two-input adder 8 is analyzed, in which by the 5th time point - written only, sampling noise, if. preliminary decision made right. If the preliminary decision is not accepted correctly, then at the outputs of the last t-bit two-input adder 8 there will be a signal corresponding to the sum of the noise and error samples. In this case, algebraic addition signals are generated in decision block 5, applied to the AND block, 10 block, as well as the result correction signals. This process is repeated until, while in the last t.p.

j

0 5 0

five

five

5 5

154

By the common two-input adder 8, the magnitude of the sample in absolute value will not be less than the value.

Claims (3)

1. The device for compensation of intersymbol interference of multi-level signals in data transmission channels,. containing in series Analog-to-digital converter, a unit for comparing multilevel inputs and reference signals and a first decision unit, a unit for generating multilevel reference signals, the first input of which is connected to the outputs of an analog-digital converter, and outputs for connecting to the second inputs of a unit for comparing multilevel input and reference signals, characterized in that, in order to improve the accuracy of the intersymbol interference correction, a preliminary storage unit is inserted in series into it; a preliminary decision storage unit; A preliminary decision, a second decision block, whose inputs are connected to the second inputs of a comparison unit for multilevel input and onopmix signals, and an output connected to the second input of a multilevel reference signal generation unit, the third input of which is connected to the first output of the first decision unit, the second output of which is connected to the second input of the preliminary decision correction unit, you, whose stroke is connected to the fourth input of the multilevel reference signal formation unit, the third outputs of the multilevel comparison unit O input and reference signals are connected to inputs of the storage unit preliminary. solutions. 2. The device according to claim 1, characterized in that the block for comparing multilevel input and reference signals contains serially connected T1 -discharge two-input Totalizers, an odd number of which is equal to the number of analyzed samples of the input signal, while the first inputs of the first This two-input adder are the first inputs of the comparison unit for multi-level input and reference signals, the second inputs of which are the second inputs of each nz t-bit two-input adders, the outputs (n + +1) of the oldest bits of the central, -discharge two-input adder are the first outputs of the comparison unit of the multi-level input and reference signals, the second inputs of which are the outputs of the last Fri-discharge two-input adder and the third outputs are the outputs of the n bits of the gp-bit dvzo: input adder preceding the central, 3. The device according to claim 1, characterized in that the block for generating multi-level reference signals comprises serially connected sample calculation block SEND.} tfiuf.Z W 5a. 6 ". From 5 / g. four O / Sfl-1. 9 From S / r. S (puf.3 Compiled by Sh. Evn and Editor A. Revin Tehred O. Gortvay; Proofreader L. Pilipenko Order 2662/58 Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 the impulse response, the input of which is the first input of the multilevel reference signal generation unit, 5 a weight modification sample block of the impulse response and a switching unit, the tTi-bit output of which is the output of the multilevel reference signal generation unit, the second input of which is the combined input of the weight modification block of the selection of the pulse response and the second of the switching unit input, the third the input, which is the third input of the multilevel reference signal generation unit, the fourth input of which is the third input of the sample modification weight block of the impulse response. . ffS / r- 5 ten ; g  t trofl.Z