CN111353118B - Method of squaring and corresponding circuit for squaring - Google Patents
Method of squaring and corresponding circuit for squaring Download PDFInfo
- Publication number
- CN111353118B CN111353118B CN201811563874.2A CN201811563874A CN111353118B CN 111353118 B CN111353118 B CN 111353118B CN 201811563874 A CN201811563874 A CN 201811563874A CN 111353118 B CN111353118 B CN 111353118B
- Authority
- CN
- China
- Prior art keywords
- selector
- square
- input end
- square root
- opened
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Data Mining & Analysis (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Algebra (AREA)
- Complex Calculations (AREA)
Abstract
The invention relates to a square opening method and a corresponding circuit for square opening, wherein the coefficient of each digit in the square root of the square number to be square-opened is calculated in sequence by means of false seeking, the corresponding square root is finally obtained, the corresponding circuit for square opening executes the operation steps in the method, the square opening operation can be effectively carried out on binary numbers, and in the circuit, the square opening calculation of the square number to be square-opened can be realized by adopting a comparator, an adder, a subtracter and a shift register to carry out shift and addition and subtraction operations on the square number to be square-opened. The method for square opening and the corresponding circuit for square opening can be used for directly calculating the square opening of the integer in the input digital circuit, the calculation efficiency is high, the cost of the adopted circuit is lower, the operation speed is higher, and the application range is wide.
Description
Technical Field
The invention relates to the field of electronics, in particular to the field of digital circuits, and particularly relates to a squaring method and a corresponding circuit for squaring.
Background
In some digital circuits, open square computation is often involved, and methods generally adopted in performing these operations in the prior art include a real function approximation method, a newton iteration method, and other computation methods, where the real function approximation method has a low accuracy, the number of iterations of the newton iteration method is determined by an initial value and square root accuracy, and division computation is required. Some other operation methods in the prior art have the problems of being obscure or complex in calculation, so that when the method in the prior art is adopted for square-opening calculation, high requirements are imposed on hardware of calculation. Sometimes, when the open square operation is performed, an open square module of floating point is also used, which often occupies more resources, and the requirement on a computing chip is higher, the cost is very high, and the computing speed is slower.
Disclosure of Invention
The invention aims to overcome at least one of the defects in the prior art and provide a square opening method with high operation speed, simple structure and low cost and a corresponding circuit for square opening.
To achieve the above object, or other objects, a method of open square and a corresponding circuit for open square according to the present invention are as follows:
the method for square opening in the digital circuit is mainly characterized by comprising the following steps:
(1) Determining the number n of bits of binary square number x to be opened;
(2) Sequentially solving coefficients on each bit in square root y of binary square number x to be opened from high bit to low bit by adopting an assumption method; the coefficient of each digit in the square root y is determined by the remainder r calculated in the previous time i The sum of the two highest digits of (2) is taken as a calculation basis, if the remainder r obtained by the previous calculation i If the sum of the highest two bits of the square root y is greater than 0, determining that the coefficient of the number of bits in the square root y calculated at present is equal to 1, if the remainder r obtained from the previous calculation i If the sum of the highest two bits in the square root y is equal to 0, determining that the coefficient of the number of bits in the square root y currently calculated is equal to 0, wherein, when determining the coefficient of the highest number of bits in the square root y, the square number x to be opened is adopted as the remainder r obtained by the previous calculation i ；
(3) And multiplying the coefficient on each bit in the square root y by the corresponding weight, and adding to obtain the square root y of the final square number to be opened.
Preferably, the step (2) includes the steps of:
(21) Judging the remainder r of previous calculation corresponding to the number of bits in the square root y of the current calculation i Whether the sum of the highest two bits of (a) is greater than 0;
(22) If the remainder r of the previous calculation corresponding to the number of bits in the square root y of the current calculation i If the sum of the highest two bits of said square root y is greater than 0, determining that the coefficient of the number of bits in said square root y of said current calculation is equal to 1; otherwise, determining that the coefficient of the number of bits in said square root y of said current calculation is equal to 0;
(23) Multiplying the coefficient of the number of bits in the square root y calculated currently by the value of the number of bits corresponding to the coefficient, and squaring the value to obtain a squared value corresponding to the number of bits in the square root y calculated currently;
(24) The remainder r obtained by the previous calculation i Subtracting a numerical value obtained after squaring corresponding to the number of bits in the square root y calculated currently to obtain a remainder obtained by calculation currently;
(25) Taking the remainder obtained by the current calculation as the remainder r obtained by the new previous calculation i Substituting the above step (21) for calculating a coefficient of a next digit adjacent to the digit in the square root y currently calculated until the value of the coefficient at each digit in the square root y is found, and continuing with the subsequent step (3).
Preferably, the step (1) further comprises the following steps:
(0.1) inputting the square number x to be opened into a digital circuit.
More preferably, if the number x of squares to be opened inputted into the digital circuit is not a binary number, the steps (0.1) and (1) further include the following steps:
(0.2) converting said square number to be opened x into said binary square number to be opened x.
The square opening circuit is mainly characterized in that the square number x to be opened is a binary number, and the circuit comprises a first adder, a second adder, a third adder, a first selector, a second selector, a third selector, a fourth selector, a first comparator, a second comparator, a third comparator, a first shift register, a second shift register, a third shift register, a fourth shift register, a fifth shift register, a first subtracter, a second subtracter and an AND gate;
the square number x to be opened is input to the input end of the first shift register, the output end of the first shift register is connected with the first input end of the second comparator, the second input end of the second comparator is input with 1, and the output end of the second comparator is simultaneously connected with the first input end of the second selector and the first input end of the third selector;
the output end of the first adder is connected with the first input end of the first selector, the second input end of the first selector is input with 0, the output end of the first selector is simultaneously connected with the second input end of the first adder and the first input end of the first comparator, the second input end of the first comparator is used for inputting a threshold value set by a user, and the output end of the first comparator is simultaneously connected with the feedback end of the first selector and the second input end of the second selector;
the second input end of the third selector is connected with the output end of the first subtracter, the third input end of the third selector is connected with the output end of the second subtracter, and the fourth input end of the third selector is connected with the output end of the AND gate;
the first input end of the first subtracter is connected with the output end of the third shift register, the second input end of the first subtracter is used for receiving the square number x to be opened, and the input end of the third shift register is used for receiving the square root y of the square number to be opened, which is obtained in the first iteration state;
the output end of the third selector is connected with the first input end of the third comparator;
the input end of the fourth shift register is used for receiving the square root of the current square number to be opened obtained in other iteration processes when the non-initial iteration state is reached, the output end of the fourth shift register is connected with the first input end of the third adder, the second input end of the third adder is input with 1, the output end of the third adder is connected with the input end of the fifth shift register, and the output end of the fifth shift register is connected with the second input end of the third comparator;
the two input ends of the AND gate are respectively connected with the output end of the first comparator and the output end of the third comparator;
the output end of the third comparator is connected with the third input end of the second selector;
the fourth input end of the second selector is input with 0, the fifth input end of the second selector is input with 1, the sixth input end of the second selector is connected with the output end of the second adder, and the seventh input end of the second selector is connected with the output end of the second shift register;
the output end of the second selector is connected with the first input end of the second adder, the input end of the second shift register and the first input end of the fourth selector at the same time, the second input end of the fourth selector inputs 0, and the third input end of the fourth selector is connected with the output end of the first comparator;
the output end of the fourth selector is used for outputting the square root y of the final square number to be opened.
Preferably, the first selector, the second selector and the fourth selector are all provided with a reset end.
By adopting the square opening method and the corresponding circuit for square opening, the coefficient of each digit in the square root of the number of squares to be opened is sequentially calculated through the hypothesis method, and the corresponding square root is finally obtained, so that the square opening operation can be effectively carried out on binary numbers. In the corresponding circuit for square opening, the square opening calculation of the square opening number can be realized by adopting a comparator, an adder, a subtracter and a shift register to shift and add and subtract the square opening number, the hardware cost for executing the steps in the square opening method is lower, the operation is convenient and the application range is wide.
Drawings
Fig. 1 is a schematic diagram of a circuit for open square in an embodiment of the invention.
FIG. 2 is a schematic diagram of the workflow of a circuit for open square in an embodiment of the invention.
Fig. 3 is a simplified workflow diagram of a circuit for open square in another embodiment of the invention.
Reference numerals
1 first adder
2 first selector
3 first comparator
4 first shift register
5 second comparator
6 second selector
7 second adder
8 second shift register
9 third shift register
10 first subtracter
11 second subtracter
12 third selector
13 AND gate
14 fourth shift register
15 third adder
16 fifth shift register
17 third comparator
18 fourth selector
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to specific embodiments.
The method for open square in digital circuit, wherein the method comprises the following steps:
(0.1) inputting the square number x to be opened into a digital circuit;
when the square number x to be opened, which is input into the digital circuit, is not a binary number, converting the square number x to be opened into the binary square number x to be opened, and then performing the subsequent step (1), otherwise, directly continuing the subsequent step (1);
(1) Determining the number n of bits of binary square number x to be opened;
(2) Sequentially solving coefficients on each bit in square root y of binary square number x to be opened from high bit to low bit by adopting an assumption method; the coefficient of each digit in the square root y is determined by the remainder r calculated in the previous time i The sum of the two highest digits of (2) is taken as a calculation basis, if the remainder r obtained by the previous calculation i If the sum of the highest two bits of the square root y is greater than 0, determining that the coefficient of the number of bits in the square root y calculated at present is equal to 1, if the remainder r obtained from the previous calculation i If the sum of the highest two bits in the square root y is equal to 0, determining that the coefficient of the number of bits in the square root y currently calculated is equal to 0, wherein, when determining the coefficient of the highest number of bits in the square root y, the square number x to be opened is adopted as the remainder r obtained by the previous calculation i The method specifically comprises the following steps:
(21) Judging the remainder r of previous calculation corresponding to the number of bits in the square root y of the current calculation i Whether the sum of the highest two bits of (a) is greater than 0;
(22) If the remainder r of the previous calculation corresponding to the number of bits in the square root y of the current calculation i If the sum of the highest two bits of said square root y is greater than 0, determining that the coefficient of the number of bits in said square root y of said current calculation is equal to 1; otherwise, determining that the coefficient of the number of bits in said square root y of said current calculation is equal to 0;
(23) Multiplying the coefficient of the number of bits in the square root y calculated currently by the value of the number of bits corresponding to the coefficient, and squaring the value to obtain a squared value corresponding to the number of bits in the square root y calculated currently;
(24) The remainder r obtained by the previous calculation i Subtracting a numerical value obtained after squaring corresponding to the number of bits in the square root y calculated currently to obtain a remainder obtained by calculation currently;
(25) Taking the remainder obtained by the current calculation as the remainder r obtained by the new previous calculation i Substituting the step (21) for calculating a coefficient of a next digit adjacent to the digit in the square root y currently calculated until the value of the coefficient at each digit in the square root y is obtained, and continuing the subsequent step (3);
(3) Multiplying the coefficient on each bit in the square root y by the corresponding weight, and adding to obtain the square root y of the final square number to be opened
The principle of the hypothesis method adopted in the above method is demonstrated below by taking a 32-bit unsigned number as an example of the square number x to be opened:
when the square number x to be opened is a 32-bit unsigned number, the square root of the square number x to be opened is y, then the binary expression of the square number x to be opened and the binary expression of the square root y of the square number x to be opened are as shown in the following formula 1:
wherein a is 31 、a 30 、……、a 0 Coefficients of the respective bits of the 32-bit square to be opened, b 15 、b 14 、b 0 The coefficients of the individual bits of square root y of the square number x to be opened, respectively.
Assuming that the sum of the highest 2 digits of the number of squares x to be opened is m, i.e. m=a 31 ×2+a 30 。
When m > 0, if b is assumed 15 =0, then y=b 14 ×2 14 +b 13 ×2 13 +...+b 1 ×2 1 +b 0 ×2 0 When b n ＝1，a 31 ＝0，a 30 ＝1，a 29 ＝a 28 ＝…＝a 0 When=0, y is obtained 2 Conclusion of < x. At this time, it can be determined that: when m > 0, b 15 =1. Similarly, when m=0, b 15 =0. By the method, an evolution result which is relatively similar to the square root y and is obtained after the first evolution can be obtained, but the evolution result is not a final evolution result, and the final evolution result can be obtained only by one iteration in the calculation process. The first evolution is followed by r n Representing the remainder of the nth iteration calculation, the initial input value of which is x i (i is the number of iterations, i=1, 2, 3 … …). In the first iterative calculation, because b 15 Is determined, at this time, the remainder r obtained after the first iterative calculation can be known 1 ：
r 1 ＝x-(b 15 ×2 15 ) 2 ＝x-b 15 ×2 30 (2)
In the above description, the judgment of the value of the coefficient of the highest order in the square root y is described, and after the coefficient of the highest order in the square root y is determined, the corresponding remainder r is obtained 1 Correspondingly, the method can correspondingly obtain the coefficients corresponding to other digits of the square root y and the remainder obtained after corresponding counting, namely, the value of the coefficient on each digit in the square root y can be determined after 16 iterations, and finally, the square root of the square number to be opened is calculated. The step of developing the binary number to be squared in the method can be realized by adopting a circuit which is applicable to squaring operation on binary numbers, and if the number to be squared is decimal or other binary numbers, the number to be squared can be firstly converted into binary numbers in other modes and then calculated.
The circuit for open square of the present invention is designed based on the principle of bit-by-bit cycle, and a 32-bit unsigned number is also explained below as an example:
first, it is determined that the number x of to be opened is a few digits, in this embodiment, the number x of to be opened is 32 digits, and the square root of the number x of to be opened is y, and then the binary expression of the number x of to be opened and the binary expression of the square root y of the number x of to be opened can be similarly represented by the above formula 1:
let the highest 2-bit number of the square number x to be opened be m, i.e. m=a 31 ×2+a 30 。
When m > 0, if b is assumed 15 =0, then y=b 14 ×2 14 +b 13 ×2 13 +...+b 1 ×2 1 +b 0 ×2 0 When b n ＝1，a 31 ＝0，a 30 ＝1，a 29 ＝a 28 ＝...＝a 0 When=0, y is obtained 2 Conclusion of < x. At this time, it can be determined that: when m > 0, b 15 =1. Similarly, when m=0, b 15 =0. By the method, an evolution result which is relatively similar to the square root y and is obtained after the first evolution can be obtained, but the evolution result is not a final evolution result, and the final evolution result can be obtained only by one iteration in the calculation process. The first evolution is followed by r n Representing the remainder of the nth iteration calculation, the initial input value of which is x i (i is the number of iterations, i=1, 2, 3 … …). In the first iterative calculation, because b 15 Is determined, at this time, the remainder r obtained after the first iterative calculation can be known 1 ：
r 1 ＝x-(b 15 ×2 15 ) 2 ＝x-b 15 ×2 30 (2)
And so on, can be obtained:
remainder r obtained by second iterative calculation 2 ：
Remainder r obtained by third iterative calculation 3 ：
Since the method for realizing the open square in the digital circuit is realized by adopting the hardware structure, in order to be convenient for better executing the method, the remainder r obtained by the n-th iterative calculation is calculated according to the calculation result n The general formula of (C) is shown as formula 5:
r n ＝r n-1 -b 15-(n-1) ×2 32-2n ×(b 15 ×2 n +b 14 ×2 n-1 ...+b 15-(n-2) ×2 2 +1) (formula 5);
b in formula 5 15-(n-1) ×2 32-2n ×(b 15 ×2 n +b 14 ×2 n-1 ……+b 15-(n-2) ×2 2 +1) is expressed as cmp, and it is known from equation 5 that when the square number to be opened of 32 bits is calculated, the final square result, that is, square root y of square number to be opened x can be obtained after 16 iterative calculation processes.
Through the above mode, through one-time iterative calculation, 0 and 1 values of each bit of the square root y are sequentially determined from high to low, and finally the final accurate square root y is obtained, wherein each iteration is a process of approaching to the final value.
In this embodiment, the circuit for open square of the present invention includes a first adder 1, a second adder 7, a third adder 15, a first selector 2, a second selector 6, a third selector 12, a fourth selector 18, a first comparator 3, a second comparator 5, a third comparator 17, a first shift register 4, a second shift register 8, a third shift register 9, a fourth shift register 14, a fifth shift register 16, a first subtractor 10, a second subtractor 11, and an and gate 13;
the square number to be opened is input to the input end of the first shift register 4, the output end of the first shift register 4 is connected with the first input end of the second comparator 5, the second input end of the second comparator 5 is input with 1, and the output end of the second comparator 5 is simultaneously connected with the first input end of the second selector 6 and the first input end of the third selector 12;
the output end of the first adder 1 is connected with the first input end of the first selector 2, the second input end of the first selector 2 is input with 0, the output end of the first selector 2 is simultaneously connected with the second input end of the first adder 1 and the first input end of the first comparator 3, the second input end of the first comparator 3 is used for inputting a threshold value set by a user, and the output end of the first comparator 3 is simultaneously connected with the feedback end of the first selector and the second input end of the second selector 6;
a second input terminal of the third selector 12 is connected to an output terminal of the first subtractor 10, a third input terminal of the third selector 12 is connected to an output terminal of the second subtractor 11, and a fourth input terminal of the third selector 12 is connected to an output terminal of the and gate 13;
the first input end of the first subtracter 10 is connected with the output end of the third shift register 9, the second input end of the first subtracter 10 is used for receiving the square number to be opened, and the input end of the third shift register 9 is used for receiving the square root of the square number to be opened obtained in the first iteration state;
the output end of the third selector 12 is connected with the first input end of the third comparator 17;
the input end of the fourth shift register 14 is configured to receive the square root of the current square to be opened obtained in other iterative processes when the non-initial iterative state is received, the output end of the fourth shift register 14 is connected to the first input end of the third adder 15, the second input end of the third adder 15 is input 1, the output end of the third adder 15 is connected to the input end of the fifth shift register 16, and the output end of the fifth shift register 16 is connected to the second input end of the third comparator 17;
the two input ends of the and gate 13 are respectively connected with the output end of the first comparator 3 and the output end of the third comparator 17;
the output end of the third comparator 17 is connected with the third input end of the second selector 6;
the fourth input terminal of the second selector 6 is input with 0, the fifth input terminal of the second selector 6 is input with 1, the sixth input terminal of the second selector 6 is connected with the output terminal of the second adder 7, and the seventh input terminal of the second selector 6 is connected with the output terminal of the second shift register 8;
the output end of the second selector 6 is connected with the first input end of the second adder 7, the input end of the second shift register 8 and the first input end of the fourth selector 18 at the same time, the second input end of the fourth selector 18 inputs 0, and the third input end of the fourth selector 18 is connected with the output end of the first comparator 3;
the output of the fourth selector 18 is used for outputting the square root of the final number of squares to be opened.
In the above embodiment, the first selector, the second selector, the third selector and the fourth selector are all provided with a reset terminal, and the specific structure thereof can be shown in fig. 1.
The shift register and the selector adopted in the invention are all common digital logic devices, and the working function requirement of the circuit can be realized without special setting.
The working process of the circuit is further described below with reference to fig. 2, and the working process of the circuit for squaring in this embodiment is described by taking the squaring of the fixed point number of 32 bits as an example:
(1) First, the number is input to the input of the first shift register.
In the initial state, the value of the remainder r is the value of the number x to be opened, the second selector selects 0 as the initial value of the square root y, the first shift register shifts the highest 2 digits m of the number x to be opened by 30 digits to the right and the shift quantity is represented by n, wherein the shift quantity n is determined by the digits of the number x to be opened, the shifted digits n is obtained by subtracting 2 digits of the number x to be opened, for example, if the 16 digits are calculated to be opened, the highest 2 digits m of the number x to be opened is shifted to the right by 14 digits; at this time, the step of initializing the variables in the flow of fig. 2 is completed;
(2) Determining whether the highest 2-bit number m of the number x to be opened is greater than or equal to 1 by a second comparator, wherein m can be determined to be 0 if the highest 2-bit number m is not greater than or equal to 1, and m is determined to be 0 if the highest 2-bit number m is not greater than or equal to 1 (namely, the second comparator performs the judging step of the total m of fig. 2 > =1), wherein the second comparator of the circuit is used for judging the current value of the judged bit of the number x to be opened, judging the adjacent 2-bit numbers in each iteration process, and the judged numbers are not repeatedly judged;
(3) When m=1, continuing the subsequent step (4), otherwise continuing the subsequent step (6);
(4) Determining the most significant bit of square root y to be 1 (i.e., y=1 in the flowchart);
(5) Shifting the square root y left by 30 bits by a third shift register (since the number n of shifts is 30 in the first iteration, shifting the square root y left by 30 bits, in the subsequent iteration, shifting the bit to be calculated of the square root y left by the corresponding n bits), then outputting the value to a first subtracter, and subtracting the value output by the third shift register by the number x to be opened to obtain a remainder r obtained after the first iteration 1 (i.e., r=x- (y) in fig. 2<<n) completing the first iteration process;
(6) Then, controlling the count of i in the iterative calculation process by the first selector, wherein i represents the number of iterations, and when the first iterative calculation is performed, the first selector performs assignment on i through 0 input by the second input terminal of the first selector (i.e. the operation step of i=0 in fig. 2);
(7) Judging the iteration times by a first comparator, and confirming whether the next iteration is needed to be continued or not; in this embodiment, since the number of to-be-opened 32 bits is calculated, only 15 iterations are needed, and at this time, the user may set the second input end of the first comparator to be 15 (i.e. the determining step of i <15 in fig. 2); if i <15 is judged, continuing the subsequent step (8), otherwise, determining that all iterative calculations are completed, and performing the subsequent step (16);
(8) In the subsequent iteration process, the first selector feeds back the current i value to the first adder, the first input end of the first adder inputs 1, and for each iteration, the i value is subjected to 1 adding operation (i.e. the i++ operation step in fig. 2), and the total flag1 represents the comparison condition of the current i value and the set threshold value in the iteration process;
(9) The shift number n at this time is subjected to an operation of subtracting 2 (i.e., an operation step of n=n-2 in fig. 2), and 2 digits after the 2 digits calculated at this time in the number of to-be-opened are prepared for calculation;
(10) Shifting the square root y obtained at this time by one bit left by a second shift register (i.e., y=y < <1 operation step in fig. 2);
(11) Shifting the square root y obtained at this time by one bit left by a fourth shift register, adding 1 to the square root y after shifting left by 1 bit by a third adder, shifting the square root y after adding 1 to n bits by a fifth shift register (the value of n=the total number of digits of the number to be opened- (2×the current iteration number)), and finally outputting cmp (i.e. cmp= ((y < < 1) +1) < < n in fig. 2);
(12) The third comparator judges whether the current remainder output by the third selector is larger than or equal to the value of cmp output by the fifth shift register in the current iteration number (namely, the judging step of r > =cmp in fig. 2), the flag3 signal output by the third comparator represents the comparison result of remainder r > =cmp in the iteration process, and the third selector controls the transformation of remainder r in the iteration process;
(13) If the current remainder is greater than or equal to the cmp value output by the fifth shift register in the current iteration times, continuing the subsequent step (14), otherwise, returning to the step (7), determining whether the y value calculated in the iteration is correct or not through the judging step, and if not, returning to the step (7) to calculate the result of the iteration again;
(14) Performing a 1-addition operation (i.e., an operation step of y++ in fig. 2) on the square root y obtained at this time by a second adder;
(15) Obtaining a remainder value r of the current iteration (i.e. an operation step of r=r-cmp in fig. 2), and then returning to the step (7) to perform the next iteration until all iteration steps are completed, and performing a subsequent step (16);
(16) The fourth selector outputs the final square root y, i.e. output y_out (i.e. the return operation in fig. 2).
Before the final output result, the AND gate in the circuit can judge the iteration times i and the correctness of the remainder obtained in the iteration process, and only if all the iteration processes are completed and the remainder obtained in the iteration process is correct, the fourth selector can output the final square root y.
The above operation process can be directly implemented by the circuit for square opening in the present embodiment, and in the whole square opening calculation process, the circuit for square opening sequentially determines whether the value on each bit of the square root is 0 or 1 from the higher order bit to the lower order bit sequentially through each iteration, and finally determines the final y value by completing all iterations.
The circuit for open square in the invention is generally only suitable for open square of fixed point number, if open square operation of floating point number is to be realized, the input end of the first shift register in the circuit is connected with a first floating point fixed point conversion module, the output end of the fourth selector is connected with a second floating point fixed point conversion module, and calculation of floating point number can be realized. The first floating point fixed point conversion module is used for converting the floating point form square number to be opened into the fixed point form square number to be opened; the second floating point fixed point conversion module is used for converting the square root of the square number to be opened from a fixed point form to a floating point form. The first floating point fixed point conversion module and the second floating point fixed point conversion module can be realized by adopting a circuit module in the prior art, or can be manually converted into fixed point numbers from floating point numbers when numerical values are input, and then the calculated fixed point numbers are manually converted into the floating point numbers.
When the floating point number is calculated, the following formula is taken as a conversion principle, the decimal part existing in the floating point number is converted into an integer by combining with the first floating point fixed point conversion module, and then the evolution operation is carried out:
then, the square root Y is obtained by performing square calculation on the square root Y by using the hardware of the square-division circuit for the fixed point number square-division part in the above embodiment, and then recovering the fractional part of the square number by using the second floating point fixed point conversion module, so as to obtain the final square root Y, and the operation steps can be shown in fig. 3.
By adopting the square opening method and the corresponding circuit for square opening, the coefficient of each digit in the square root of the number of squares to be opened is sequentially calculated through the hypothesis method, and the corresponding square root is finally obtained, so that the square opening operation can be effectively carried out on binary numbers. In the corresponding circuit for square opening, the square opening calculation of the square opening number can be realized by adopting a comparator, an adder, a subtracter and a shift register to shift and add and subtract the square opening number, the steps in the square opening method are executed, the hardware cost is lower, the operation is convenient, and the application range is wide.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (6)
1. A method for open square in a digital circuit, said method comprising the steps of:
(1) Determining the number n of bits of binary square number x to be opened;
(2) The binary system is obtained from the high order to the low order by adopting the hypothesis methodCoefficients on each bit in square root y of the number of squares x to be opened; the coefficient of each digit in the square root y is determined by the remainder r calculated in the previous time i The sum of the two highest digits of (2) is taken as a calculation basis, if the remainder r obtained by the previous calculation i If the sum of the highest two bits of the square root y is greater than 0, determining that the coefficient of the number of bits in the square root y calculated at present is equal to 1, if the remainder r obtained from the previous calculation i If the sum of the highest two bits in the square root y is equal to 0, determining that the coefficient of the number of bits in the square root y currently calculated is equal to 0, wherein, when determining the coefficient of the highest number of bits in the square root y, the square number x to be opened is adopted as the remainder r obtained by the previous calculation i ；
(3) And multiplying the coefficient on each bit in the square root y by the corresponding weight, and adding to obtain the square root y of the final square number to be opened.
2. The method of open square for digital circuits according to claim 1, wherein said step (2) comprises the steps of:
(21) Judging the remainder r of previous calculation corresponding to the number of bits in the square root y of the current calculation i Whether the sum of the highest two bits of (a) is greater than 0;
(22) If the remainder r of the previous calculation corresponding to the number of bits in the square root y of the current calculation i If the sum of the highest two bits of said square root y is greater than 0, determining that the coefficient of the number of bits in said square root y of said current calculation is equal to 1; otherwise, determining that the coefficient of the number of bits in said square root y of said current calculation is equal to 0;
(23) Multiplying the coefficient of the number of bits in the square root y calculated currently by the value of the number of bits corresponding to the coefficient, and squaring the value to obtain a squared value corresponding to the number of bits in the square root y calculated currently;
(24) The remainder r obtained by the previous calculation i Subtracting a numerical value obtained after squaring corresponding to the number of bits in the square root y calculated currently to obtain a remainder obtained by calculation currently;
(25) Taking the remainder obtained by the current calculation as the remainder r obtained by the new previous calculation i Substituting the above step (21) for calculating a coefficient of a next digit adjacent to the digit in the square root y currently calculated until the value of the coefficient at each digit in the square root y is found, and continuing with the subsequent step (3).
3. The method of open square applied in a digital circuit according to claim 1, wherein said step (1) is preceded by the step of:
(0.1) inputting the square number x to be opened into a digital circuit.
4. The method of claim 3, wherein if the number x of squares to be opened inputted to the digital circuit is not a binary number, the steps (0.1) and (1) further comprise the steps of:
(0.2) converting said square number to be opened x into said binary square number to be opened x.
5. A circuit for squaring implemented using the method of claim 1, wherein the number of squares to be squared x is a binary number, the circuit comprising a first adder, a second adder, a third adder, a first selector, a second selector, a third selector, a fourth selector, a first comparator, a second comparator, a third comparator, a first shift register, a second shift register, a third shift register, a fourth shift register, a fifth shift register, a first subtractor, a second subtractor, and an and gate;
the square number x to be opened is input to the input end of the first shift register, the output end of the first shift register is connected with the first input end of the second comparator, the second input end of the second comparator is input with 1, and the output end of the second comparator is simultaneously connected with the first input end of the second selector and the first input end of the third selector;
the output end of the first adder is connected with the first input end of the first selector, the second input end of the first selector is input with 0, the output end of the first selector is simultaneously connected with the second input end of the first adder and the first input end of the first comparator, the second input end of the first comparator is used for inputting a threshold value set by a user, and the output end of the first comparator is simultaneously connected with the feedback end of the first selector and the second input end of the second selector;
the second input end of the third selector is connected with the output end of the first subtracter, the third input end of the third selector is connected with the output end of the second subtracter, and the fourth input end of the third selector is connected with the output end of the AND gate;
the first input end of the first subtracter is connected with the output end of the third shift register, the second input end of the first subtracter is used for receiving the square number x to be opened, and the input end of the third shift register is used for receiving the square root y of the square number to be opened, which is obtained in the first iteration state;
the output end of the third selector is connected with the first input end of the third comparator;
the input end of the fourth shift register is used for receiving the square root of the current square number to be opened obtained in other iteration processes when the non-initial iteration state is reached, the output end of the fourth shift register is connected with the first input end of the third adder, the second input end of the third adder is input with 1, the output end of the third adder is connected with the input end of the fifth shift register, and the output end of the fifth shift register is connected with the second input end of the third comparator;
the two input ends of the AND gate are respectively connected with the output end of the first comparator and the output end of the third comparator;
the output end of the third comparator is connected with the third input end of the second selector;
the fourth input end of the second selector is input with 0, the fifth input end of the second selector is input with 1, the sixth input end of the second selector is connected with the output end of the second adder, and the seventh input end of the second selector is connected with the output end of the second shift register;
the output end of the second selector is connected with the first input end of the second adder, the input end of the second shift register and the first input end of the fourth selector at the same time, the second input end of the fourth selector inputs 0, and the third input end of the fourth selector is connected with the output end of the first comparator;
the output end of the fourth selector is used for outputting the square root y of the final square number to be opened.
6. The circuit for squaring according to claim 5, wherein the first selector, the second selector, and the fourth selector are each provided with a reset terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811563874.2A CN111353118B (en) | 2018-12-20 | 2018-12-20 | Method of squaring and corresponding circuit for squaring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811563874.2A CN111353118B (en) | 2018-12-20 | 2018-12-20 | Method of squaring and corresponding circuit for squaring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111353118A CN111353118A (en) | 2020-06-30 |
| CN111353118B true CN111353118B (en) | 2023-09-19 |
Family
ID=71196695
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811563874.2A Active CN111353118B (en) | 2018-12-20 | 2018-12-20 | Method of squaring and corresponding circuit for squaring |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111353118B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113407235B (en) * | 2021-06-28 | 2022-07-08 | 珠海一微半导体股份有限公司 | Operation circuit system and chip based on hardware acceleration |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1081851A (en) * | 1976-06-11 | 1980-07-15 | Otakar A. Horna | Pseudo rms value circuit |
| EP0351242A2 (en) * | 1988-07-15 | 1990-01-17 | Fujitsu Limited | Floating point arithmetic units |
| JP2005102279A (en) * | 1996-03-06 | 2005-04-14 | Matsushita Electric Ind Co Ltd | Data receiver |
| CN1671090A (en) * | 2004-03-19 | 2005-09-21 | 华为技术有限公司 | An apparatus for square root computation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8812575B2 (en) * | 2010-07-06 | 2014-08-19 | Silminds, Llc, Egypt | Decimal floating-point square-root unit using Newton-Raphson iterations |
-
2018
- 2018-12-20 CN CN201811563874.2A patent/CN111353118B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1081851A (en) * | 1976-06-11 | 1980-07-15 | Otakar A. Horna | Pseudo rms value circuit |
| EP0351242A2 (en) * | 1988-07-15 | 1990-01-17 | Fujitsu Limited | Floating point arithmetic units |
| JP2005102279A (en) * | 1996-03-06 | 2005-04-14 | Matsushita Electric Ind Co Ltd | Data receiver |
| CN1671090A (en) * | 2004-03-19 | 2005-09-21 | 华为技术有限公司 | An apparatus for square root computation |
Non-Patent Citations (4)
| Title |
|---|
| M.纳莱 ; 莫莎 ; .一个高速运算器的逻辑设计.计算机研究与发展.(06),全文. * |
| 吴保芳.用于过程控制的浮点数快速开平方程序.电子技术应用.1989,(02),全文. * |
| 左全生.二进制数平方根计算的一种快速算法.《电测与仪表》.2002,第39卷(第6期),第44-47页. * |
| 张小鸣,王正洪,朱正伟.高精度定点数平方根汇编子程序的实现原理.江苏石油化工学院学报.2003,(04),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111353118A (en) | 2020-06-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20180373977A1 (en) | Optimized neuron circuit, and architecture and method for executing neural networks | |
| CN110377267B (en) | Signed number adder/subtracter based on probability calculation concentrated sequence | |
| CN111813371B (en) | Floating point division operation method, system and readable medium for digital signal processing | |
| CN102231101B (en) | Divider and division processing method | |
| JP2021517301A (en) | Stochastic rounding logic | |
| CN111353118B (en) | Method of squaring and corresponding circuit for squaring | |
| CN112035796A (en) | Optimization method of integrated circuit-oriented ultra-low-delay integer power calculation circuit | |
| JPH01144122A (en) | Dividing circuit | |
| JPH0480815A (en) | Absolute value computing circuit | |
| US5181184A (en) | Apparatus for multiplying real-time 2's complement code in a digital signal processing system and a method for the same | |
| CN110677138B (en) | FIR filter based on error-free probability calculation | |
| CN112783469A (en) | Method and device for executing floating-point exponential operation | |
| US20200192633A1 (en) | Arithmetic processing device and method of controlling arithmetic processing device | |
| CN110705196B (en) | Error-free adder based on random calculation | |
| CN115809707A (en) | Quantum comparison operation method and device, electronic device and basic arithmetic assembly | |
| JP6948735B2 (en) | Pulse density modulation method and pulse density value signal conversion circuit | |
| US4159529A (en) | Fibonacci code adder | |
| CN111190571A (en) | Modular multiplication circuit based on binary domain expansion and control method thereof | |
| CN115879554B (en) | Quantum modulus square operation method and device, electronic device and modulus arithmetic component | |
| CN115033205B (en) | Low-delay high-precision constant value divider | |
| US11163531B2 (en) | Multiply and accumulate (MAC) unit and a method of adding numbers | |
| US20210365239A1 (en) | Logarithm calculation method and logarithm calculation circuit | |
| Liu et al. | A pipelined sign-error LMS adaptive filter architecture with low computational complexity | |
| CN220208247U (en) | Division operation circuit | |
| JP2002014804A (en) | Ternary digital circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 214135 -6, Linghu Avenue, Wuxi Taihu international science and Technology Park, Wuxi, Jiangsu, China, 180 Applicant after: China Resources micro integrated circuit (Wuxi) Co.,Ltd. Address before: 214135 Jiangsu city of Wuxi province Wuxi Linghu Taihu International Science Park Road No. 180 -22 Applicant before: WUXI CHINA RESOURCES SEMICO Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |