CN115033205B - Low-delay high-precision constant value divider - Google Patents
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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Abstract
The invention discloses a low-delay high-precision constant value divider, which is used for a pre-division moduleAt a utilization value of 2 N Each bit in the N-bit unsigned dividend of-1 performs pre-division calculation on the divisor to obtain a quotient coefficient array and a remainder coefficient array, and the pre-division module has no hardware overhead; the remainder calculation module is used for multiplying the remainder coefficient array by the corresponding bit in the dividend to obtain a remainder array, and performing addition calculation on the remainder array to obtain a remainder and a remainder carry array; and the quotient number calculation module is used for multiplying the quotient number coefficient array by the corresponding bit in the dividend to obtain a quotient number array, and performing addition calculation on the quotient number array and the remainder carry number array to obtain the quotient number. The method converts the fixed value division into the realization of using an addition network by calculating the quotient coefficient and the remainder coefficient corresponding to each bit of the dividend in advance, and the calculation of the quotient and the remainder is carried out simultaneously, thereby not only providing ultra-low delay output, but also completely retaining the precision information by providing the remainder, and having the characteristics of high speed and low delay.
Description
Technical Field
The invention relates to the technical field of digital circuits, in particular to a low-delay high-precision constant value divider.
Background
In digital circuit design, when mathematical operations are performed on data, a design scheme meeting requirements is usually required to be provided according to operations to be realized, and particularly when division operations are required to be performed. If the dividend is not constant, the most classical solution is shift subtraction, which involves two-part logic, comparison and subtraction, with a very simple structure but with a large delay. In addition, a general divider design based on a Goldschmidt algorithm is adopted, multiple iterations are needed in the operation process, the structure is complex, and the method is suitable for floating point number operation. If the dividend is a fixed value, the general solution is to convert the division operation into a multiplication operation, and then take a fixed value of the multiplication result to obtain the final result. If the dividend bit width is narrow, the method can also be realized by a table look-up method.
When division operation is needed to be carried out on a fixed value, a general divider is adopted to carry out operation, so that delay is too large, or complexity is too high to meet design cost requirements. A general divider is not typically used to handle division of a constant value in systems with special requirements for low latency. If the division operation is converted into the multiplication operation, the calculation result inevitably has an error caused by decimal truncation under the condition that the dividend is not the power of 2.
Based on this, a new solution is needed.
Disclosure of Invention
The invention mainly aims to provide a low-delay high-precision constant value divider.
In order to achieve the above object, the present invention provides a low-latency high-precision constant value divider for division operation in which a dividend is an unsigned integer with a bit width N and a divisor M is a positive integer greater than or equal to 3, the divider comprising a pre-division module, a quotient calculation module and a remainder calculation module, wherein the pre-division module is configured to utilize the value of 2 to calculate a remainder N Each bit in the N-bit unsigned dividend of-1 performs pre-division calculation on the divisor to obtain a quotient coefficient array and a remainder coefficient array, and the pre-division module has no hardware overhead; the remainder calculation module is used for multiplying the remainder coefficient array by the corresponding bit in the dividend to obtain a remainder array, and performing addition calculation on the remainder array to obtain a remainder and a remainder carry array; and the quotient number calculation module is used for multiplying the quotient number coefficient array by the corresponding bit in the dividend to obtain a quotient number array, and performing addition calculation on the quotient number array and the remainder carry number array to obtain the quotient number.
In the low-delay high-precision constant value divider provided by the invention, the pre-dividing module is used for dividing the value into 2 N -1 of the ith bit in the N-bit unsigned dividend is converted to 2 i And then carrying out division calculation with the divisor to obtain a quotient and a remainder which are respectively used as the ith element in the quotient coefficient array and the ith element in the remainder coefficient array, wherein i is a positive integer which is more than or equal to 0 and less than or equal to N-1.
In the low-delay high-precision constant value divider provided by the invention, the remainder calculation module comprises a first multiplier and a first addition network, the first multiplier is used for multiplying the remainder coefficient array by the corresponding bit in the dividend to obtain a remainder array, wherein if the corresponding bit in the dividend is the dividendIf the corresponding bit in the dividend is 1, the element corresponding to the remainder array is the corresponding coefficient in the remainder coefficient array; the first addition network comprises a k-layer addition network, the remainder array is subjected to addition operation through the k-layer addition network to obtain a remainder and a remainder carry array, and k = log 2 N。
In the low-delay high-precision constant value divider provided by the invention, in the j-th layer addition network, the remainder array L of the j-th layer addition network is firstly calculated by the following formula j _prsum[N/2 j -1：0]The value L of the a-th bit of (1) j _prsum[a]Wherein j is an integer of 0 to k, and a is 0 to N/2 j A positive integer of-1, L when j =0 0 _prsum[N-1：0]Is the array of remainders from the first multiplier when j>At 0 time
L j _prsum[a]=L j-1 _prsum[2a]+L j-1 _prsum[2a+1]
If L is j _prsum[a]If the value is larger than or equal to the divisor, the corresponding value L of the remainder carry array j C[a]=1, and L j _prsum[a]=L j-1 _[2a]+L j-1 _[2a+1]-divisor, and vice versa, the value L of the corresponding remainder carry array j C[a]=0, and L j _prsum[a]=L j-1 _prsum[2a]+L j-1 _prsum[2a+1]。
In the low-delay high-precision constant value divider provided by the invention, the quotient calculation module comprises a second multiplier and a second addition network, the second multiplier is used for multiplying the quotient coefficient array by the corresponding bit in the dividend to obtain the quotient array, wherein if the corresponding bit in the dividend is 0, the element corresponding to the quotient array is 0, and if the corresponding bit in the dividend is 1, the element corresponding to the quotient array is the coefficient corresponding to the quotient coefficient array; the second addition network comprises a k-layer addition network, the quotient array and the remainder carry array are subjected to addition operation through the k-layer addition network to obtain a quotient, wherein k = log 2 N。
In the low-delay high-precision constant value divider provided by the invention,in the j-th layer addition network, a quotient array L of the j-th layer addition network is calculated by the following formula j _pqsum[N/2 j -1：0]The value L of the a-th bit of (1) j _pqsum[a]Wherein j is an integer of 0 to k, and a is 0 to N/2 j A positive integer of-1, L when j =0 0 _pqsum[N-1：0]Is the quotient array from the second multiplier when j>At 0 time
L j _pqsum[a]=L j-1 _pqsum[2a]+L j-1 _pqsum[2a+1]+L j C[a]。
The low-delay high-precision constant value divider and the method provided by the invention have the following beneficial effects: the low-delay high-precision fixed value divider provided by the invention converts the fixed value division into the realization by using an addition network by calculating the quotient coefficient and the remainder coefficient corresponding to each bit of the dividend in advance, and the calculation of the quotient and the remainder is carried out simultaneously, so that the low-delay high-precision fixed value divider not only can provide ultra-low delay output, but also can completely reserve precision information in a manner of providing the remainder, and has the characteristics of high speed and low delay.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:
FIG. 1 is a schematic diagram of a low-latency high-precision constant-value divider according to an embodiment of the present invention;
fig. 2 is a computing network of a remainder computing module of a low-latency high-precision constant value divider according to an embodiment of the present invention;
fig. 3 is a computing network of a quotient calculating module of a low-latency high-precision constant value divider according to an embodiment of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Exemplary embodiments of the invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The general idea of the invention is as follows: aiming at the problem that the existing division design scheme is not completely applicable in a system with low delay and high calculation precision requirement, the invention provides a low-delay high-precision constant value divider.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to the drawings and the specific embodiments of the specification, and it should be understood that the embodiments and specific features of the embodiments of the present invention are detailed descriptions of the technical solutions of the present application, and are not limited to the technical solutions of the present application, and the technical features of the embodiments and examples of the present invention may be combined with each other without conflict.
An embodiment of the present invention provides a low-latency high-precision fixed value divider, which is used for division operation in which a dividend is an unsigned integer with a bit width N and a divisor M is a positive integer greater than or equal to 3, and referring to fig. 1, the low-latency high-precision fixed value divider includes:
a pre-divide module 10 using said value of 2 N Each bit of the-1N-bit unsigned dividend performs pre-division calculation on the divisor to obtain a quotient coefficient array and a quotientAn array of coefficient numbers;
and a remainder calculation module 30, configured to multiply the remainder coefficient array by a corresponding bit in the dividend to obtain a remainder array, and perform addition calculation on the remainder array to obtain a remainder and a remainder carry array.
A quotient calculation module 20, configured to multiply the quotient coefficient array by a corresponding bit in the dividend to obtain a quotient array, and perform addition calculation on the quotient array and the remainder carry array to obtain a quotient;
specifically, in an embodiment of the present invention, the dividend is an unsigned integer with a bit width of N, that is, N is an unsigned integer with 8 bits, 16 bits, 32 bits, etc., such as 8'b1111 \u1111 or 16' b1110 \u1111 \u1101 _1111, etc. The divisor M is a positive integer greater than or equal to 3.
Specifically, in one embodiment of the present invention, the utilization value of the pre-division module 10 is 2 N Pre-dividing the divisor by each bit of the unsigned number of N bits of-1 to obtain two groups of coefficients coef _ q and coef _ r, wherein coef _ q is a quotient coefficient and coef _ r is a remainder coefficient. The pre-divide module divides dividend 2 N Bit i in-1 to 2 i And then, carrying out division calculation with the divisor to obtain a quotient and a remainder which are respectively used as the ith element in the quotient coefficient array and the ith element in the remainder coefficient array, wherein i is a positive integer which is more than or equal to 0 and less than or equal to N-1. For example, taking dividend as 8-bit unsigned integer with bit width N and divisor 3 as examples, first, the value is 2 8 The dividends for-1 each bit is converted to [ (2^7), (2^6), (2^5), (2^4), (2^3), (2^2), (2^1), (2^0)](ii) a Then calculating [ (2^7), (2^6), (2^5), (2^4), (2^3), (2^2), (2^1), (2^0)]/3, the obtained quotient is used as a quotient coefficient array coef _ q [7:0]The elements of (a): [42, 21, 10,5,2,1,0,0]The remainder is used as the remainder coefficient array coef _ r 7:0]The elements (c): [2,1,2,1,2,1,2,1]The pre-divide module does not have any hardware overhead.
Specifically, in one embodiment of the present invention, as shown in FIG. 2, the pre-divide module 10 pairs a value of 2 N After pre-dividing the divisor for each bit of the N-bit unsigned integer of-1 to obtain a quotient coefficient array coef _ q and a remainder coefficient array coef _ rThe residue coefficient array coef _ r is sent to a residue calculating module, and the residue calculating module 30 is a residue calculating network composed of a first multiplier and a first adding network. And multiplying the coefficient of the remainder coefficient array by the corresponding bit in the dividend through a first multiplier, and calculating the obtained result through a first addition network to obtain the final remainder.
Further, in an embodiment of the present invention, the first multiplier is configured to multiply the remainder coefficient array by a corresponding bit in the dividend to obtain a remainder array, and the first multiplier is implemented by and logic, where if the corresponding bit in the dividend is 0, an element corresponding to the remainder array is 0, and if the corresponding bit in the dividend is 1, the element corresponding to the remainder array is a corresponding coefficient in the remainder coefficient array. For example, when the dividend is an unsigned integer 8' b 1011/1011 with a bit width N of 8 bits and the divisor is 3, the remainder coefficient array coef _ r [7:0]Is [2,1,2,1,2,1,2,1]Then the residue coefficient array L obtained by multiplying the two 0 _prsum[7:0]Is [2,0,2,1,2,0,2,1]。
Further, in an embodiment of the present invention, the first adding network includes a k-layer adding network, and the remainder array is added by the k-layer adding network to obtain a remainder and a remainder carry array, where k = log 2 And N is added. For example, as shown in fig. 2, for the case where the dividend is an unsigned integer with a bit width N of 8 bits, k =3, i.e. the first addition network comprises 3 layers. In particular, when N is not the power of 2, the design idea is the same, but the number of layers of the summing network needs to be rounded up, i.e. when N is 9, k = log 2 N needs to be rounded up to get k =4.
Further, in an embodiment of the present invention, in the j-th adder network, the remainder array L of the j-th adder network is first calculated by the following formula j _prsum[N/2 j -1：0]The value L of the a-th bit of (1) j _prsum[a]Wherein j is an integer of 0 to k, and a is 0 to N/2 j A positive integer of-1, L when j =0 0 _prsum[N-1：0]Is the remainder from the first multiplierArray of numbers when j>At 0 time
L j _prsum[a]=L j-1 _prsum[2a]+L j-1 _prsum[2a+1]
If L is j _prsum[a]If the value is larger than or equal to the divisor, the corresponding value L of the remainder carry array j C[a]=1, and L j _prsum[a]=L j-1 _prsum[2a]+L j-1 _prsum[2a+1]-divisor, and vice versa, the value L of the corresponding remainder carry array j C[a]=0, and L j _prsum[a]=L j-1 _prsum[2a]+L j-1 _prsum[2a+1]. As shown in FIG. 2, the remainder operation comprises a 3-level adder network, and in the 1 st-level adder network, the remainder array L0_ prsum [7:0 ] calculated above is input]For the first layer of the summing network, L 1 _prsum[3]=L0_prsum[7]+L0_prsum[6]=2, less than divisor, then L 1 C[3]=0，L 1 _prsum[3]=2；L 1 _prsum[2]=L0_prsum[5]+L0_prsum[4]=3= divisor, then L 1 C[2]=1，L 1 _prsum[2]=0; by parity of reasoning, L is obtained 1 _prsum[3：0]=[2，0，2，0]，L 1 C[3：0]=[0，1，0，1]；L 2 _prsum[1：0]=[2，2]，L 2 C[1：0]=[0，0]；L 3 _prsum[0]=1，L 3 C[0]And =1. Thus, a remainder L is obtained 3 _prsum[0]=1, remainder carry array L obtained in calculating remainder j C[a]Is immediately sent to the quotient calculation module.
Specifically, in one embodiment of the present invention, as shown in FIG. 3, the pre-divide module 10 pairs a value of 2 N After pre-dividing the divisor by each bit of the N-bit unsigned integer of-1 to obtain a quotient coefficient array coef _ q and a remainder coefficient array coef _ r, sending the quotient coefficient array coef _ q to a quotient calculation module, where the quotient calculation module 20 is a quotient calculation network composed of a second multiplier and a second addition network. And multiplying the coefficient of the quotient coefficient array by the corresponding bit in the dividend through a second multiplier, and calculating the obtained result through a second addition network to obtain the final quotient.
Further, in an embodiment of the present invention, the second multiplier is configured to multiply the quotient coefficient array by corresponding bits in the dividend to obtain a quotient arrayAnd the second multiplier is realized by AND logic, wherein if the corresponding bit in the dividend is 0, the element corresponding to the quotient array is 0, and if the corresponding bit in the dividend is 1, the element corresponding to the quotient array is the corresponding coefficient in the quotient coefficient array. For example, taking N as an 8-bit unsigned integer 8' b1011/1011 and a divisor of 3 as an example, the quotient coefficient array coef _ q [7:0]Is [42, 21, 10,5,2,1,0, 0]And then multiplying the two to obtain a quotient coefficient array L 0 _pqsum[7:0]Is [42,0, 10,5,2,0,0, 0]。
Further, in an embodiment of the present invention, the second addition network includes a k-layer addition network, and the quotient is obtained by performing addition operation on the quotient array and the remainder carry array through the k-layer addition network, where k = log 2 And N is added. For example, as shown in fig. 3, for the case where the dividend is an unsigned integer with a bit width N of 8 bits, k =3, i.e. the second addition network comprises 3 layers. In particular, when N is not the power of 2, the design idea is the same, but the number of layers of the summing network needs to be rounded up, i.e. when N is 9, k = log 2 N needs to be rounded up to get k =4.
Further, in an embodiment of the present invention, in the j-th addition network, the quotient array L of the j-th addition network is calculated by the following formula j _pqsum[N/2 j -1：0]The value L of the a-th bit of (1) j _pqsum[a]Wherein j is an integer of 0 to k, and a is 0 to N/2 j A positive integer of-1, L when j =0 0 _pqsum[N-1：0]Is the quotient array from the second multiplier when j>0 time L j _pqsum[a]=L j-1 _pqsum[2a]+L j-1 _pqsum[2a+1]+L j C[a]. As shown in FIG. 3, the quotient operation comprises a 3-layer addition network, and in the 1 st-layer addition network, the quotient array L calculated above is input 0 _pqsum[7:0]Sum remainder carry array L 1 C[3:0]For the first layer of the summing network, L 1 _pqsum[3]=L 0 _pqsum[7]+L 0 _pqsum[6]+L 1 C[3]=42，L 1 _pqsum[2]=L 0 _pqsum[5]+L 0 _pqsum[4]+L 1 C[2]=16; by parity of reasoning, L is obtained 1 _pqsum[3：0]=[42，16，2，1]；L 2 _pqsum[1：0]=[58，3]；L 3 _pqsum[0]=62. Thus, the quotient is obtained as 62.
In the low-delay high-precision constant value divider provided by the invention, the quotient calculation and the remainder calculation are synchronously carried out, the coefficient bit width of the remainder does not exceed the bit width of the divisor, and when the bit width of the divisor is far smaller than the bit width of the dividend, the remainder calculation is completed quickly. The number of additive network layers to compute quotient and remainder is log 2 N, when dividend bit width N is 8bit, the addition network has 3 layers, and when N is 32bit width, the addition network has 5 layers. The number of layers of the addition network increases along with the logarithm of the bit width, and in practical application, if the bit width of the dividend is wide, so that the number of layers is too much and the time sequence is difficult to meet, one-stage or multi-stage flow registers can be inserted into the addition network according to needs. For N/3,N as an 8-bit unsigned integer, the final calculation result is a quotient L 3 _pqsum[0]The remainder is L 3 _prsum[0]. The result can be obtained in one clock cycle without inserting a pipeline. Therefore, the method for calculating the quotient coefficient and the remainder coefficient corresponding to each bit of the dividend in advance through the pre-division module converts the constant value division into the realization by using an addition network, the calculation of the quotient and the remainder is carried out simultaneously, and the pre-division calculation has no hardware overhead and has the characteristics of high speed and low delay.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
Claims (5)
1. A low-delay high-precision constant value divider is used for division operation of which dividend is an unsigned integer with a bit width of N and divisor M is a positive integer more than or equal to 3, and is characterized by comprising a pre-division module, a quotient calculation module and a remainder calculation module, wherein the pre-division module is used for utilizing a value of 2 N -each bit of the N-bit unsigned dividend of 1 to said dividePre-dividing the number to obtain a quotient coefficient array and a remainder coefficient array; the remainder calculation module is used for multiplying the remainder coefficient array by corresponding bits in the dividend to obtain a remainder array, and performing addition calculation on the remainder array to obtain a remainder and a remainder carry array; the quotient number calculation module is used for multiplying the quotient coefficient array by the corresponding bit in the dividend to obtain a quotient array, and performing addition calculation on the quotient array and the remainder carry array to obtain a quotient;
the pre-divide module sets the value to 2 N The ith bit in the N-bit unsigned dividend of-1 is converted to 2 i And then carrying out division calculation with the divisor to obtain a quotient and a remainder which are respectively used as the ith element in the quotient coefficient array and the ith element in the remainder coefficient array, wherein i is a positive integer which is more than or equal to 0 and less than or equal to N-1.
2. The low latency high precision fixed value divider of claim 1, wherein the remainder calculation module comprises a first multiplier and a first summing network, the first multiplier is configured to multiply the array of remainder coefficients by corresponding bits in the dividend to obtain an array of remainders, wherein if the corresponding bit in the dividend is 0, the element corresponding to the array of remainders is 0, and if the corresponding bit in the dividend is 1, the element corresponding to the array of remainders is the corresponding coefficient in the array of remainder coefficients; the first addition network comprises a k-layer addition network, the remainder array is subjected to addition operation through the k-layer addition network to obtain a remainder and a remainder carry array, and k = log 2 N。
3. The divider of claim 2, wherein in the j-th adder network, the remainder array L of the j-th adder network is first calculated by the following formula j _prsum[N/2 j -1：0]The value L of the a-th bit of (1) j _prsum[a]Wherein j is an integer of 0 to k, and a is 0 to N/2 j A positive integer of-1, L when j =0 0 _prsum[N-1：0]Is an array of remainders from the first multiplier,when j is>At 0 time
L j _prsum[a]=L j-1 _prsum[2a]+L j-1 _prsum[2a+1]
If L is j _prsum[a]If the value is larger than or equal to the divisor, the corresponding value L of the remainder carry array j C[a]=1, and L j _prsum[a]=L j-1 _prsum[2a]+L j-1 _prsum[2a+1]-divisor, and vice versa, the value L of the corresponding remainder carry array j C[a]=0, and L j _prsum[a]=L j-1 _prsum[2a]+L j-1 _prsum[2a+1]。
4. The low-latency high-precision fixed-value divider according to claim 3, wherein the quotient calculation module comprises a second multiplier and a second addition network, the second multiplier is configured to multiply the quotient coefficient array by a corresponding bit in the dividend to obtain a quotient coefficient array, wherein if the corresponding bit in the dividend is 0, an element corresponding to the quotient coefficient array is 0, and if the corresponding bit in the dividend is 1, the element corresponding to the quotient coefficient array is a corresponding coefficient in the quotient coefficient array; the second addition network comprises a k-layer addition network, the quotient array and the remainder carry array are subjected to addition operation through the k-layer addition network to obtain a quotient, wherein k = log 2 N。
5. The low-latency high-precision constant-value divider of claim 4, wherein in the layer j addition network, the quotient array L of the layer j addition network is calculated by the following formula j _pqsum[N/2 j -1：0]The value L of the a-th bit of (1) j _pqsum[a]Wherein j is an integer of 0 to k, and a is 0 to N/2 j A positive integer of-1, L when j =0 0 _pqsum[N-1：0]Is the quotient array from the second multiplier when j>At 0 time
L j _pqsum[a]=L j-1 _pqsum[2a]+L j-1 _pqsum[2a+1]+L j C[a]。
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