SU1557681A1 - Modular code converter - Google Patents

Abstract

The invention relates to computing and can be used in systems and devices operating in modular arithmetic. The purpose of the invention is to expand the field of application by ensuring the conversion of a multi-stage modular code into a code of the previous stage. There is a periodic dependence of the residuals of the codes of the lower step on the residuals of the codes of the larger step. Therefore, it suffices to implement only one repetitive part of the correspondence table and, by subtracting certain constants, move from one part to another. The converter contains a group of blocks of elements AND 2, a group of subtractors 3 constants, a group of registers 4, a decoder 5, a trigger 6, and elements OR 7 and 9 with corresponding links. 2 ill., 2 tab.

Description

2. 1-2. To the elements And go to the subtractors 3.1-3. To and through them the original balances are recorded in the registers 4.1-4. To; since the information is received in a parallel code, then one of the inputs will necessarily have a potential 1, which simultaneously enters through the element OR 7 at the input of the setting to zero of the trigger 6. When a clock pulse arrives at the trigger recording input of the trigger, the trigger 6 is transferred to zero state and with the potential O from the direct output closes blocks 2.1-2, K of the elements I. Signals from the outputs of the registers are sent to the decoder 5, in which they are converted according to the algorithm described above; since the number 19 does not lie in the range 0-m-l, for our case 0-11-1 10, then all outputs of the decoder 5 will have potentials O, At the same time, the signals from the outputs of registers 4.i-4.K are fed to the inputs

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Claims (1)

Invention Formula A modular code converter containing a group of subtractors, constants, a group of registers and the first element OR, the outputs of the subtractors of the group constant are connected to the information inputs of the corresponding group registers, the outputs of which are connected to the information inputs of the corresponding subtractors of the group constant, the input of the initial installation of the converter is connected to the installation inputs o registers of the group whose recording resolution inputs are connected to the clock input of the converter, the termination output of which is connected to swing first OR, The relative lichayuschiis in that, in order to expand the application area by providing a multi-stage converting polar modulation code in the code the previous stage, it comprises subtracters 3. 1-3. To, in which 25 group of blocks of elements I occur, decrypts subtraction modulo from the codes constants: Rf 11 mod; R2 11 mod R3 11 mod 8., () mod S7 (4-1) mod S3 (5-4) mod. These residues correspond to the number 8, indeed, 19 mod. From the corresponding residues of the outputs of registers 4.1-4. The signals arrive at the decoder 5, in which the function corresponds to the potential 111 at the output of the decoder corresponding to a remainder equal to 8. The signal arrives at output 12, At the same time, these signals arrive at the input of the element OR 9, the output of which will be potential 1, since at one of its inputs there was potential 1. This potential is fed to input 8. At this, the conversion ends and the converter is ready for processing the following residues. torus, trigger and second element OR, the group of information inputs of the converter is connected to the first inputs of the corresponding blocks of elements AND groups, the second inputs of which are connected to the trigger output, the installation inputs to 1 and into which are connected to the input of the converter installation head with the output of the second element OR, the inputs of which are connected respectively with the outputs of the bits of the senior block of elements AND of the group, the outputs of the blocks of elements AND of the group are connected to the installation inputs of the corresponding subtractor th constants groups, which enable input connected to the input solvable Sheni recording trigger and a clock input transducer outputs Regis trench group are connected respectively to the inputs of the decoder, the outputs of which are connected with respective first input of said first OR epementa and are data pin pr ° obrazovat 50 l. 35 40 45 torus, trigger and second element OR, and the group of information inputs of the converter is connected to the first inputs of the corresponding blocks of elements AND of the group, the second inputs of which are connected to the trigger output, the inputs of the installation in 1 and in O of which are connected respectively to the input of the beginning 1 of the converter installation with the output of the second element OR, the inputs of which are connected respectively to the outputs of the bits of the senior block of elements AND of the group, the outputs of the blocks of elements of the AND group are connected to the installation inputs of the corresponding subtract The constants of the group whose resolution inputs are connected to the trigger recording input of the trigger and the converter clock input, the outputs of the group registers are connected respectively to the decoder inputs, the outputs of which are connected to the corresponding inputs of the first OR stage and are the information output of the software generator. / 0 FIG. I „