SU1697079A1 - Device for computing modulo multiplication - Google Patents

Abstract

The invention relates to automation and computing and can be used in computers and devices operating in the system of residual classes. The aim of the invention is to simplify the device. A device for multiplying modulo numbers contains a group of blocks of 3 elements AND, a group of blocks of 4 multiplication by a constant modulo, ring registers 5 and 16 of shift, a block of 8 elements OR, a counter 9, an element OR 10, elements 11, 13 and 14, an element NOT 12, block 15 of the elements AND and the encryption 17 with the appropriate links, 1 Il.

Description

The invention relates to automation and computing and can be used in computers and devices operating in the system of residual classes.

The purpose of the invention is to simplify the device.

The drawing shows a diagram of a device for multiplying modulo numbers.

The device contains the input 1 of the first factor, the input 2 of the second factor, a group of blocks 3 elements AND, a group of blocks 4 multiplied by a constant modulo, the first ring register 5 shift, the output 6 of the device, the clock input 7 of the device, the block of elements OR 8, counter 9, the element OR 10, the first element And 11, the element NOT 12, the second and third elements And 13 and 14, the block of elements And 15, the second ring register 16 shift, the encoder 17.

Blocks 4 multiplication by a constant modulo the group are implemented as in the analog.

The essence of the invention is as follows: let A be the first operand, B the second and it is necessary to carry out the operation of modular multiplication AB (mod m), where m is the module. Represent number B as B Sn-i-2n 1 + Sn-2-2n 2 + .. + + S0 2 ° (n 1092 (m-1) + 1) Then

n - 1 A B 2 A 21 Si (Si is O or 1,

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those. corresponds to the value of the corresponding bit in the binary representation of the number B). The product of the form A -21 (mod m) can be obtained by using the multiplication unit by a constant. Consequently, to obtain the result of operation А-В (mod m), it is necessary to carry out sequential tracking of numbers of the type A-2 (mod m) for those bits of the binary representation, the numbers 8, Si of which are equal to one.

Consider the operation of the device. The first ring register 5 shift consists of n binary bits (from 0th to n-1st) Second

WITH

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The circular shift register 16 consists of m binary bits (from the 0th to the m-1th). In the initial state, the units of the registers 5 and 16 are written to zero bits, and the remaining bits are zeroed at the input of the initial setup of the device (not shown in the drawing). The first factor A is fed to the inputs of blocks 4 multiplied by a constant modulo, as well as the first input of the last block of 3 elements AND groups, at the inputs of blocks 4 multiplied by a constant modulo group we get the product of the form (a-21) mod m (i n- 1 - 1), and at the third input of the last block 3 elements And we have (A-2 °) mod m A. The second factor B in the binary code goes to the corresponding second inputs of the blocks 3 elements And groups. The first inputs of the blocks of 3 elements AND groups receive a signal. From the outputs of the bits of the first ring register 5 shift. Initially, in the zero discharge de register 5 recorded unit. In the corresponding n-1st. the bit of operand B is also recorded as one. Then, through the corresponding block of elements AND 3 and through the block of elements OR 8, the number (A -2P) then goes to the pulse input of setting the number of the counter 9. The signal from the element OR 10 opens the element AND 11, and the pulses from the input 7 of the device enter the permission input the shift of the bits of the register 16 and the subtracting input of the counter 9. After (A-2n) modm pulses, the unit from the zero bit of the register 16 goes to () mod the m-th bit, and the contents of the counter 9 becomes equal to zero. Then the signal enters through element 12 at element 13. From the input 7 of the device, one pulse arrives at the input of the shift resolution of register bits 5, moving the unit from zero to the first. If in the n-2nd binary bit of the operand B is zero, the signal from element 12 enters And 13, and the unit from the first register bit 5 goes to the second. The process continues until the unit in register 5 goes into n-1-th bit. In this case, if the corresponding (zero) bit of operand B is zero, the output of element 12 is a signal that comes from element And 14 at the first input of the block of elements And 15, and the result of the modular multiplication operation, obtained in a unitary code at the outputs of the register bits 16, is received through the encoder 17, which converts it into a binary representation, in the last 6 of the device. If the zero binary bit of operand B is equal to one, the signal from AND 14 enters only when the contents of counter 9 becomes zero, i.e. after the last addition.

FORUMAWLAH AND ISLANDS

A device for multiplying modulo numbers, containing a group of blocks of elements And, the first and second ring registers.

shift, block of elements OR, counter, element NOT, from the first to the third elements AND and the block of elements AND, and the bits of the first circular shift register are connected to the first inputs of the corresponding

blocks of elements AND groups whose outputs are connected to the corresponding inputs of the block of elements OR, the clock input of the device is connected to the first inputs of the first and second elements AND, the output of the element is NOT connected to the second input of the second element AND, the output of the third element And is connected to the first input of the block of elements AND , in order to simplify the device, it contains a group of units of multiplication by a constant modulo, the OR element and an encoder, with the input of the first device multiplier connected to the inputs of multiplication units by band modulo, input bit inputs

The second device multiplier is connected to the second inputs of the corresponding blocks of elements AND groups, the outputs of multiplication blocks by a constant modulo the group are connected respectively to the third inputs of blocks of elements AND, except for the last group, the input of the first factor of the device is connected to the third input of the last block of elements AND groups, output the block of elements OR is connected to the installation input of the counter, the outputs of the bits of which are connected to the corresponding inputs of the element OR, the output of which is connected to the input of the element NOT and with the second input of the first element And, the output of which

Connected to the subtracting input of the counter and to the shift enable input of the second ring shift register, the bit outputs of which are connected to the corresponding inputs of the encoder, the output of which is connected to the second input of the AND block whose output is the device output, the output of the last bit of the first ring shift register and the output of the element is NOT connected respectively to the first and

the second inputs of the third element And, the output of the second element And is connected to the input of the resolution, the shift of the first ring shift register.

Claims (1)

5 claims A device for multiplying numbers modulo containing a group of blocks of AND elements, first and second ring shift registers U, a block of OR elements, a counter, an element NOT, first to third AND elements and a block of AND elements, and the outputs of the bits of the first ring shift register are connected with the first inputs of the corresponding 15 blocks of elements AND groups, the outputs of which are connected to the corresponding inputs of the block of elements OR, the clock input of the device is connected to the first inputs of the first and second elements AND, the output of the element 20 is NOT connected to the second by the course of the second AND element, the output of the third AND element is connected to the first input of the block of AND elements, characterized in that, in order to simplify the device, it contains a group of 25 blocks of multiplication by a constant modulo, an OR element, and an encoder, and the input of the first factor of the device connected to the inputs of the units of multiplication by a constant modulo the group, the inputs of the bits of the input 30 of the second factor of the device are connected to the second inputs of the corresponding blocks of elements And groups, the outputs of the units of multiplication by a constant modulo the group are connected respectively Accordingly, with the third inputs of the AND block of elements, except for the last group, the input of the first factor of the device is connected to the third input of the last block of AND elements, the output of the OR block is connected to the setting input of the counter, the bit outputs of which are connected to the corresponding inputs of the OR element, the output which is connected to the input of the element NOT and to the second input of the first element AND, the output of which 45 is connected to the subtracting input of the counter and to the shift enable input of the second ring shift register, outputs in which they are connected to the corresponding inputs of the encoder, the output of which is connected to the second input of the block of elements I. The output of which is the output of the device, the output of the last bit of the first ring shift register and the output of the element are NOT connected to the first and 55 second inputs of the third element And, the output of the second element And is connected to the shift enable input of the first annular shift register.