SU1218470A1 - Device for translating codes - Google Patents

Abstract

The device relates to automation and computing and can be used in data conversion systems without changing the order of their following or the amount of information, in particular in devices converting the antenna’s angular position and time represented in the binary-ten-sixth, counting system. binary number system. The device allows, along with the conversion of a binary-six-hexadecimal code of the angular values and time into a binary code, the implementation of and scaling of their lower-order bits. The device includes the first shift register 1, six logical blocks 2-7, two blocks 8 and 9 elements AND, block 10 elements OR, the second shift register 11, block 12 adders, two elements And 13 and 16, two elements NOT 14 and 15, two elements OR 17 and 19, a trigger 18, a shift control unit 20, inputs 21 and 22 devices, an output 23 of the device on which the converted binary code is generated, and a triggering input 24 of the device. 1 hp ff, 2 ill. Ipuf.i

Description

I

The invention relates to automation and computing, as well. specifically for devices for data conversion, and can be used in real-time 1-DEFECT antenna control devices for converting the antenna angular position and time presented in a binary-ten-sixth number system (degrees, hours, minutes, seconds in binary number system with a different price of a unit i of the least significant bit.

The aim of the invention is to enhance the functionality of the device by providing the conversion of binary-hex-hexadecimal code to binary code with scaling.

Fig, 1 shows a functional diagram of the device; Fig. 2 is a diagram of the shear control unit.

The device for converting codes contains the first shift register 1, the first 2, the second 3, the third 4, and the fourth 5 tetrad shapers, the first and second 7 triad shapers, the first 8 and second 9 blocks of elements AND, the 10 elements of the OR block, the second shift register 11, block 12 of adders, the first element AND 13, the first element NOT 14, the second element NOT 15, the second element AND 16, the first element OR 17, the trigger 18, the second element OR 19, the shift control unit 20, the inputs 21, 22 of the device, device output 23, which triggers device input 24.

The shift control unit 20 comprises a pulse generator 25, a single pulse generator 26, the first element AND 27, a pulse shaping amplifier 28, the element OR 29, the one-shot 30, the first trigger 31, the element NO 32, the element EXCLUSIVE OR 33, the second element AND 34, the third element And 35, the second trigger 36.

The device works as follows.

After switching on, registers 1 and 11 are reset to the shift control unit 20, and the input of the first element NOT 14, connected to the input of the second element OR 17, receives a signal from the last one. After 184701

Consequently, the operation of the first AND 13 element by the signal from the first is forbidden. element 14 and the operation of the second element AND 16 5 is permitted through the element OR 17.

The first register 1 shifts and converts the binary-to six-hexadecimal code recorded from the information inputs of 21 into 10 binary with the help of formers of 2-7 tetrads. The algorithm of work of formers 2,3,4,5 tetrads is as follows:

four

Y, X. X, VX X;

 Xj.x, vx, .x.x, v .x a X, 4 V 5

Y X, X, jX, Y X, j X,

where x, xj, x, are input signals

in order of increasing bit number;

The output signals in order of increasing no. measure size

The algorithm of work of shapers of 6.7 triads is as follows:

Y

t x,

Xj X, X, Xj X, j Xj X “V X X

where x XX is the output signals in order of increasing the bit number;

F1) W.We and single signals in order of increasing the bit number.

The code is converted by overwriting the code generated at the outputs of the 2-7 triad shapers and tetrads through the first block of 8 elements AND and the block of 10 elements OR in register 1 using clock pulses received from block 20 of the shift control at the input of the first register 1 .

The device is started by a Start signal from input 24,

arriving at the shift control unit 20, while

H bits) from inputs 21 through the second block 9 elements AND and the block 10 elements OR are recorded in the first register 1 using a recording pulse coming from the Shift control unit 20 to the second inputs of the second block 9 elements I. At the same time using the same momentum

trigger 18 remembers the signal

0 the need to scale the information (logical 1 if there is information about time and logical O with information about i coordinates), and the second register 11, in (1-3) and bit, records the signal of logical 1 with which the cycles are controlled device operation

The first cycle of the device operation is the conversion of a binary-detich-sixty-sixth code into a binary code and the second one is a code scaling.

The shift control unit 20 includes the Record mode in the first register 1 and the Shift mode, in the second register 11, generates clock pulses that convert information from the binary-hexadecimal code to the binary code in the first register 1 and shift the information in the second register 11. In this case, the resulting binary code arrives from the low-order bit of the first register shift 1 to the information input of the second register II, and the logical 1 in the (and Z) -th bit of the second register 11 is shifted towards the low-order bit. When set after the 20th pulse) low-order bit .in 1, the shift control unit 20 switches the first register

1 in shift mode. After the transition of information from the low bit of register II through the element And 16 and. the OR 17 element in the high-order bit of the first register 1, the shift control unit 20 produces a logical signal O at the input of the element NOT 14, thus completing the first cycle of operation associated with the conversion, the operation of the element AND 13 is permitted, and through the element SHIII 17 the operation of the element is prohibited And 16. The following situations may arise:

trigger 18 — in state I, the input information does not require scaling), therefore, the operation of the AND 13 element is prohibited (through the NOT 15 element), and the operation of the AND 16 element is allowed through the IPI element 17, in this case the information without scaling through the AND 16 element goes to first register 1

trigger 18 - in the state O (input information about the angles and tre

scaling), so the information from the second register 11 through the block 12 adders, the elements And 13, the element OR 19 in the sequential

5 code enters the first register 1.

The information converted to binary code after the first cycle of operation is in the second register 1 1 and the second cycle begins. 10 work. In the case of a time code conversion in the second cycle, the information from the second register 11 through the element 16 and the element OR 19 enters the first register 1 and

15 according to logic 1 at the output of the lower bit of the first register 1, the shift control unit 20 stops the clock frequency and at the outputs of the bits of the first register

20, a transformed binary code is set up, which is outputted at the output 23 of the code conversion device.

When converting the angular values, the signals must be scaled, therefore, the block 12 adders receive information from the first, third, fifth, ninth, twelfth, nineteenth, and twenty:

3Q of the second bits of the second register 11, which provides information from the output of the block 12 adders in the sequential code.

A device for converting a code converts a hexadecimal binary-binary code to an accuracy of one angular second, with the 2 tetrad shaper forming units of seconds, forming

tel 6 triads - ten seconds seconds, 40

worldlord 3 tetrad - units of minutes

the shaper is 7 triads - tens of minutes, the shaper is 4 tetrad-units of degrees (hours), the shaper is 5 tetrads - tens of degrees (hours). The number of elements in the first block is 8 elements And is equal to h -1, and in the second block 9 elements And, a block of 10 elements ШШ and the number of bits in the first 1 and second 11 registers corresponds to the number of bits of the output code h

35

45

50

Claims (2)

Invention Formula 55 1. A device for converting. Codes that contains the first shift register, tetrad shapers and the shift control unit, the first the output of which is connected to the control-. The first entry of the first shift register, in contrast, is that, in order to expand the functionality of the device by converting the binary-hexadecimal code into binary code with scaling, it introduced a trigger, NOT elements, elements OR , And elements, block of adders, blocks of And elements, block of IL elements, two triad generators and a second shift register, the control input of which is connected to the second output of the shift control block, the information input is combined with the first input of the block control shift and connected to the output of the first bit of the first shift register, the outputs of the subsequent bits of which, except the last, are connected to the corresponding inputs of the first tetrad shaper, the first triad taper, the second triad shaper, the third and fourth tetrad shaper, output the last bit of the first shift register is connected to the first input of the first element AND of the first block of elements AND, the first inputs of the subsequent elements AND of the first block of elements AND oedineny the outputs sootvetstvzposchih formers tetrads and triads, the first input of the second block of elements and combined with the C-input of the flip-flop and connected to the third output of the shift control unit, a fourth output is connected to second inputs of AND gates of the first block elements. And, the outputs of the First and Second blocks of elements And are connected to the corresponding inputs of the block of elements OR, the outputs of which are connected to the corresponding first information inputs of the first shift register, first, third. the fifth, ninth, twelfth, nineteenth and twenty-second outputs of the second shift register are connected to the corresponding inputs of the block of adders, the output of which is connected to the first input of the first element I, the second input of which is connected to the output of the first the NO element, the third input is with the output of the second element NO, the first input of the first element OR is combined with the input of the first element NOT and connected to the fifth output of the shift control unit, the second input of the first element OR combined with the input of the second element NOT and 010 with the trigger code, the first input of the second element I is connected with the second input of the shift control unit and connected to the output of the first bit of the second shift 5 registers, the second input of the second element AND is connected to the output of the first OR element, the output to the first input of the second OR element, the second input of which is connected to the first element AND, the output to the second information input of the first shift register, the second inputs elements And the second block of elements, And and D - trigger input 5 are the inputs of the device, the outputs of the first shift register, except the first and last, are - (from the output of the device, the third input of the shift control unit 0 is the trigger input of the device. 2. The device according to claim 1, characterized in that the shear control unit consists of a pulse generator, a single pulse generator, the first AND element, a pulse shaping amplifier, the OR element, a one-shot, the first trigger, the NO element, the EXCLUSIVE element OR, the second and third elements And the second trigger, the output of the pulse generator is connected to the first outputs of the generator of a single pulse and the first element And, the outputs of which are connected respectively to the first and. the second inputs of the OR element, 5 —the input of the first trigger is combined with the input of the one-shot and connected to the output of the generator of a single pulse; the 3rd input of the second trigger is combined with the first output of the element EXCLUSIVE OR and connected to the output of one vibrator; the first input of the second element is connected (With the direct output of the first trigger,; The inverse output of which is connected to five 0 five the first input of the third element is And, the second input of which is the first input of the shift control unit, 1 is the input of the first trigger connected to the input of the element HB and is the second input of the shift control unit, R is the inputs of the first and second triggers are combined and connected to the output pulse amplifier, the element output is NOT connected to the second input of the second element, And the output of the third element And is connected to the K-input of the second trigger, the direct output of which is connected to the second input of the first And, the second input of the single pulse generator is the third input of the shift control unit, the outputs of the second AND element, the OR element, the one-shot, the SPACK element THREE OR and the direct output of the first trigger are respectively the first, second, third, quarter and fifth outputs of the shift control unit. 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