SU1674364A1 - Analog-to-digital converter - Google Patents

Abstract

The invention relates to a measurement technique and can be used in single-signal detection systems. The aim of the invention is to improve the accuracy of the representation of the shape of the measured signals. The purpose of the invention is achieved in that a device containing an amplitude-digital converter, the input of which through amplifiers is connected to a transform signal bus, a memory unit, a control unit, a counter and a generator, has a delay line input, the input of which is a Start bus, and exit bus "Request". 1 hp f-ly, 3 ill.

Description

This invention relates to a measurement technique and can be used in single-signal detection systems.

The aim of the invention is to improve the accuracy of the representation of the shape of the measured signals.

FIG. 1 shows the analog-digital converter circuit; in fig. 2 - time diagrams of his work; in fig. 3 is a control block diagram.

The analog-to-digital converter contains bus 1 of the signal to be converted, amplifier 2, bus 3 Start, amplitude-digital converter 4, delay line 5, bus 6 Inquiry, memory block 7, control block 8, bus 9 Preset, bus 10, Read clock, output bus 11, counter 12 and generator 13.

When a signal arrives at the Start 3 bus (time point to - Figs. 2 and 3), after the delay time ta (Fig. 2, and), the device is set to the Read mode. As a result, information about the last 2 m (m — the address bus width of the memory block 7) of the amplitude-digital converter 4 or the amplitude of the input signal at the time moments Гь + 1з- (2m-1) is read from memory block 7 etc. to + tjj, where the step etc. is the sampling of the input signal.

In the initial state, the device is in the Read mode, a sequence of pulses on the bus 10 A read clock is not supplied, the generator 13 forms a sequence of pulses (Fig. 2, c), the control unit 8 blocks the supply of pulse signals to the gates of the converter 4 and the write 7 memories.

The Measurement mode (Fig. 2, b) is transferred to the device by applying a pulse (Fig. 2. a) to bus 9 Preset. Control unit 8 in accordance with sequential VI

WITH

about &

Stew (Fig. 2, c) of the pulses of the generator 13 generates gating pulses (Fig. 2, d) of the converter 4, records (Fig. 2, e) of the memory block 7 and clock pulses (Fig. 2, e) of the counter 12, providing the operation of the device when converting and memorizing the input signal (Fig. 2, g). With the arrival of the signal (Fig. 2, h) on the bus 3 Start (time point to) in time r3 on the delay line 5 (Fig. 2, i) it will set the control unit 8 to the Read mode and go to the Bus 6 Request (Fig. 2, and). In the Read mode, gating pulses (Fig. 2, d) of the transducer 4 and the records (Fig. 2, e) of the memory block 7 are not generated, and the clock pulses (Fig. 2, e) of the counter 12 are formed in accordance with the pulses (Fig. 2, k), arriving at tire 10 Read cycle. At the moment the device enters the Read mode, the state of the code combination K (K 0.1., 2m-1) at the output of the counter reflects the address of the element of memory block 7, which contains information about the last (2nd) th sampling point of the input signal corresponding time t.0 + Xs (up to t, d). When the first pulse is applied to bus 10, the read clock state of the code combination at the output of counter 12 will take the following value K + 1 at and O at K 2m-1, and the output sampling point of memory 7 will receive information about the first sampling point of the input signal which corresponds to the moment of time b + 1s-1d (2m-1). When the next pulses are fed to the bus 10 Read cycle, the output bus 11 will receive information on the following sampling points (Fig. 2, l). In the case of a ratio

ty, d (2m - 1),

The Ti-duration of the information part of the input signal) the device allows the conversion of the input signal in the area preceding the device start signal (time t0).

When pulses are removed from the bus 10 Tact reading, the device returns to its original state.

The control unit 8 may be implemented according to the scheme shown in FIG. 3

Block 8 contains a RS-flip-flop 14. element 2IL-AND 15, element OR 16, the first delay line 17 and the second delay line 18.

The control unit 8 operates as follows.

In the initial state (Read mode), trigger 14 is in a state with

logical o about inverse output. The elements 2ILI-15 and OR 16 prohibit the passage from the output of the generator 13 pulse sequence

the first, second and fourth outputs of block 8, and from the inverse output of trigger 14, the third output of block 8 receives a logic level O (read permission from memory block 7). From the bus 10 of block 8, the passage of read cycles (Fig. 2, k) through the element 2ILI-I 15 and the delay line 17 to the fourth output of block 8 (Fig. 2, e) is allowed. When a pulse is applied (Fig. 2, a) to the bus. Preset of the block 8, the trigger 14 is set to

state with logic level 1 at the inverse output (Fig. 2, b). The pulse sequence (Fig. 2, c) from block 13 will go through element 16 OR to the first output (Fig. 2, d) and with a delay ri on the line

delays 18 to the second output (fig. 2, e) of block 8, and through element 2ILI-I 15 with delay T2 on delay line 17 to the fourth output of block 8 (fig. 2, e). Delay t is selectable based on time

converting converter 4, and time n - m / 2 - taking into account the time of setting the address in memory block 7. The third output of block 8 receives level G, blocking the reading from block 7 of information memory.

When a pulse is applied (Fig. 2, i) to the bus 6, the block 8 is reset.

When the device operates in asynchronous mode, the signal to the bus 3 Start can

be formed using a level discriminator, the input of which is connected to the output of amplifier 2, and the output to the bus 3 Start.

40

Claims (2)

1. An analog-to-digital converter containing an amplifier, the input of which is the bus of the signal to be converted and the output connected to the information input amplitude-digital converter, the output of which is connected to the first input of the memory unit, the second input of which is connected to the output of the counter, control input of the amplitude of the digital-to-digital converter connected to the first output of the control unit, the second and third outputs of which are connected to the third and fourth inputs of the memory unit, respectively; the fourth output of the control unit is connected to the input counter, the first input is with the output of the pulse generator, the second, third and fourth inputs of the control unit are Request, Preset and Read cycle, respectively, the output of the memory unit is output bus, which in order to improve the accuracy of waveforms of the measured signals; a delay line is entered in it, the input of which is the Start bus, and the output is the Request bus. 2. The converter according to claim 1, that is, that the control unit is executed on the trigger, the elements OR, 2IL-I and the first and second delay lines, the outputs of which are the second and the fourth output of the block, and the inputs are connected respectively to the output of the OR element, which is the first output of the block, and the output of the 2ILI-I element, the first input of which is the fourth input of the block, the second input of the first group is connected to the inverse output of the trigger and is the third output of the block, the first input of the second group is connected to the forward output of the trigger and is connected to the first input of the element OR, the second input of which is connected to the second input of the second group of element 2IL-I and is the first input of the block, the R- and S-inputs of the trigger are the second and third inputs of the block, respectively. 15 56 9bm11 ° 1 I i i / USU 9U9.Z d / moves Rig.Z