SU1388997A1 - Residual class system code-to-position code converter - Google Patents

Abstract

The invention relates to computing and is intended to convert a code from a system of residual classes into a position code. The purpose of the invention is to reduce hardware costs. The goal is achieved by the fact that the code converter of the system of residual classes into a position code containing four registers 1–4 shift, subtractor 7, adder – subtractor 5, three adders 6,24,25, shaper 8 additional code, switch 9 of the system base residual classes, switch II, synchronization unit 12, code comparison circuit 13, two triggers .14,15, four elements AND 16-19, EXCLUSIVE OR 20, two delay elements 21,22, contains the third delay element 23 with the corresponding connections mi 1 PC. with S (L

Description

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The invention relates to a computing technique, is intended to convert a code from a system of residual classes into a positional code, and can be used in digital automation and telemechanics systems.

The aim of the invention is to reduce hardware costs. : The drawing shows the scheme | converter code system residual classes | in the positional code.

Residual class system code converter into positional code with

It drives a sequence of clock pulses at its outputs. The sync pulse from the first output of the synchronization unit 12 is fed to the control input for entering information of shift registers 1-3 and also to the inputs of the elements 18 and 19. By this signal, the initial information is inputted into parallel shift binary registers 1,2 and 3 codes, and triggers 14 and 15 are set to the states that determine the mode of operation of the converter. Register 1 shift contains 2p + 1

holds registers 1-4 shift, adder-15 bit, and registers 2 and 3 shift n

 subtractor 5, adder 6, subtractor

I 7, frmi 8 additional

code, switch 9 bases of the system | topics of residual classes, input 10 of the range of representation of numbers 20

{converter, switch 11, block

| 12 synchronization circuit 13 comparison

codes, triggers 14 and 15, elements

II 16-19, an element of suicide or 20,

; elements 21-23 delay, adders 25

; 24 and 25, groups of informational inputs 26 and 27 of the converter, input 28

: start converter,

Block 12 synchronization scheme 13

bits, where n - the number of bits of the representation of residues about, and in the bases of P and P, the system of residual classes.

Register 4 shift contains m times the series, where m p.

Parallel n-bit binary codes of residuals oi, and oi are read off responsibly from information inputs 26 and 27 and written to shift registers 2 and 3, respectively. A parallel 2n-bit binary code P ,, - P of the number representation range is read from input 10 and written to

code comparisons and shaper 8 up to-30 shift register 1, the older 2n + 1 st additional code are implemented and function identically to the prototype.

The converter of the code of the system of residual classes to the positional code works as follows. 35

In the initial state, the triggers 14, 15 are in the zero state, in which they are set as a result of the previous conversion cycle. 40

Using switch 9, the binary code of base P is set, systems of residual classes are set, and input 10 sets the range of which the bit is in the zero state.

The comparison circuit 13 codes the two n-bit parallel binary codes of the residuals acting on the information inputs 26 and 27 of the device, respectively, and generates the output 1 at

The signal 1 at the output of the code comparison circuit 13 opens the element AND 18, through which the pulse passes from the first output of the synchronization unit 12 and sets the trigger 14 to one state.

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12

residual class systems

Pj 6N - 1; N 2S m is a natural number equal to v, where

The base switch 9 of the residual class system connects one of the outputs of the bits of the shift register 4 to the input of the delay / clock element 23 and to the first input of the adder 24.

The converter is started up by applying a signal 1 to the converter start input 28, according to which the synchronization unit 12 is formed, where n is the number of digits for representing the residuals, and in the bases P and P of the residual classes system.

Shift register 4 contains m bits, where m p.

The parallel n-bit binary codes of the residuals oi and oi are read from the information inputs 26 and 27, respectively, and written to registers 2. and 3 shifts, respectively. A parallel 2n-bit binary code P ,, - P of the number representation range is read from input 10 and written to

shift register 1, senior 2n + 1

the bit of which is in the zero state.

The comparison circuit 13 codes two n-bit parallel binary codes of residuals acting. on the information inputs 26 and 27 of the device, respectively, and generates the output signal 1 when,.

The signal 1 at the output of the code comparison circuit 13 opens the element AND 18, through which the pulse passes from the first output of the synchronization unit 12 and sets the trigger 14 to one state.

The element ENTITUDING OR 20 compares the lower bits of the binary codes of the residuals oi, and Ы acting on the first information inputs 26 and 27, respectively. When various signals act in the lower bits of the residual binary codes, the output of the EXCLUSIVE OR 20 element produces a signal 1 which opens the AND 19 element. The pulse from the first output of the synchronization unit 12 passes through the AND 19 element and sets the trigger 15 to the one state.

Under the influence of clock pulses from the second output of synchronization block 12, the binary codes of the residuals are shifted, starting with the lower order bits, with the outputs of the registers 2 and 3 of the shift, respectively. The subtractor 7 completes the sequential subtraction from the serial binary code of the remainder oij of the serial binary code of the remainder oi, and the output of the subtractor 7 forms the serial binary code of the residual difference, which, starting with the least significant bit, goes to the information input of the imager - 8 additional code.

The additional code generator 8 converts the additional residual difference code oi .. - (v, into the direct code if its control input receives the signal I from the zero output of trigger 14, or passes without changing the forward code of the residual difference when trigger 14 is in a single state. Thus, at the output of the shaper .8 of the additional code, a direct code is formed of the absolute value of the residual difference (oij) - oi, /, which through element 16 enters, starting from the lower order, at the information input of the register 4 shift. n, two, ..., t clocks at the outputs of the first, second, ..., t-th bits of the 4 shift register, under the action of pulses, from the second output of the synchronization block 12, starting with the lower bits, the serial binary code residual differences. Since the delay of a sequential code by one clock cycle is equivalent to multiplying by two, then at the outputs of the first, second, ..., t-th bits of the shift register 4, respectively, successive binary codes of 2 joi - oi i / are formed , ..., 2 / cij - oi, /. One of these values is selected by switch 9 of the base of the system of residual classes. For example, if the base of the system of residual classes Pf 6N + 1, then the output of the i + 1th digit of the shift register 4 is connected by switch 9 to the input of the delay element 23 and the first input adder 24. In this case, the output of the switch 9 generates a sequential binary code of the magnitude -oi, /, which is delayed by the delaying element 23 per clock.

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five

which is equivalent to multiplying this value by two. Thus, at the output of the delay element 23, a serial binary code of 2 oil / 5 is formed, which is summed, starting with the lower bits, in the adder 24 with the serial binary value code, -o, /, generated at the output of the switch 9 of the base system of residual classes . At the output of the adder 24, a sequential binary code of the magnitude b-2 joly oi, t, which is summed, starting with the least significant bits, is formed in the adder 25 with the serial binary code of the value / 6i -oi, / generated at the output of the And 16 element. adder 25 generates a successive binary code for the product of the base of the system of residual classes on absolutism, the magnitude of the difference between the residuals P./oi, -ab, /. After the clock cycles, after the converter is started, a zero signal is generated at the third output of the synchronization unit 12, the blocking subtractor 7 is generated, and at the fifth output of the synchronization unit 12, a signal 1 is generated that installs on the input. reset the shaper 8 additional code to its original state. From the output of the adder 25, the serial binary code of the product arrives, starting with the low-order bit, to the first input of the adder-subtractor 5. The totalizer-subtractor 5 is set to the summing mode, if trigger 14 is in the zero state, or to the subtraction mode, when trigger 14 is in a single state. The consecutive residual binary code is shifted, starting with the lower bit, under the action of pulses from the second output of the synchronization unit 12 to the code of the delay unit 21 per clock. Delay element 21 provides a one-digit shift in the serial binary code of the remainder relative to the serial binary product code. and those. implements the operation of multiplying the binary code of the remainder by two. The serial binary code of the 2oi2 value comes from the output of the delay element 21 to the second input of the adder-subtractor 5, which, depending on the summation or subtraction mode, forms the serial binary code of the i l

5 13 The switch 1 1 connects the output of the shift register 1 to the input of the adder 6, if the trigger 15 is in the unit state, or connects the input of the adder 6 to the output of the delay unit 22 when the trigger 15 is in the zero state. Element And 17 blocks the input, delay element 22, if trigger 14 is in the zero state, or connects: the output of the I shift register to the input of delay element 22, when trigger 14 is in the unit state.

After starting the converter bottom

 An identical code of Pj is shifted under the action of pulses from the second | output of synchronization unit 12 from the register: shift 1 and, starting from the least significant bit, enters through the switch; the switch 11 to the input of the adder 6 in the case of the single state trigger 15. | In this case, at the output of the adder 6 |, a serial binary code of the value P, P + 2y t P, x: n / oii oi, / is formed, which is equal to twice the value of the transformed number.

When the trigger 15 is in the zero state, and the trigger 14 is in the single state, the binary code P, - P is shifted from the shift register 1 through the AND 17 element, the tact delay element 22 and the switch 11 to the | adder input 6. Element 22 delays per clock provides a shift by ONE bit of the serial binary code of the value P, P with respect to the serial binary code generated at the output of the totalizer-subtractor 5, i.e., it implements the operation of multiplying the serial binary code by two .. In this case, the output of the adder 6 is formed mc sequential binary code of 2P, - Р + 2ci ,, - Р ,. ., which is equal to twice the value of the converted number. In particular, when the triggers 14 and 15 are in the zero state, the AND element 17 is closed by the direct output signal of the trigger 14 and the output 1 is mutated by the 1 1 1 zero binary code. The output of the adder 6 in this case generates a binary code of the value 2o (, 2 + PV / oi If which is equal to twice the value of the transformed number.

Sequential binary code of the converted number from the output of the sum

7

Section 6 is written, starting from the lower bit, into the shift register 1 under the action of pulses, arriving, from the second output of the synchronization unit 12.

After 2n + 1 clock after the converter is started, the binary code of the converted number is fixed in shift register 1. The register size of shift 1 2p + is chosen so that

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d

0 5

thirty

35

40

45

50

55

The lower bit of the binary code of the converted -number (the second bit of the value of the military value of the converted number) at the end of the conversion cycle was in the first bit of the shift register 1. In addition, after 2p + 1 clock cycle, after triggering the converter, the triggers 14 and 15 pulse to the zero state from the fourth output of the synchronization unit 12, the synchronization unit 12 is reset, and the conversion cycle ends.

Claims (1)

Invention Formula The converter of the residual classes system code into a position code contains the first, second, third, and fourth shift registers, a subtractor, a totalizer, a subtractor, three summers, an additional code generator, a switch of the base of the residual classes system, a switch, the first and second triggers, first, second., third and fourth elements AND, first and second elements of delay, EXCLUSIVE OR element, a code comparison circuit and a synchronization unit, the converter start input connected to the synchronization block start input and, the first output of which is connected to the resolution input inputs of the first, second and third shift registers, the second output of the synchronization unit is connected to the shift resolution inputs of the first, second and third shift registers, the third output of the synchronization unit is connected to the permission input of the subtractor and with the first input of the first element And, the fourth output of the Synchronization block is connected to the inputs for setting the first and second triggers to zero, the fifth output of the synchronization block is connected to the reset input of the additional driver o code whose output is dinene with the second input of the first element I, the output of the first element of the delay connected to the first information input of the totalizer subtractor, the resolution and subtraction resolution inputs of which are connected respectively to the direct and inverse outputs of the first trigger, the output of the subtractor subtractor connected to the input of the first component of the first an adder whose second input is connected to the output of the switch, the output of the adder is connected to the information input of the first shift register, the group of data input inputs of which is connected to the input assigning the range of representation of the converter number, the output of the first shift register is connected to the first input of the second element AND and the first information input of the switch, the control input of which is connected to the direct output of the second trigger, the direct output of the first trigger is connected to the second input of the second element And, the output of which through the second delay element is connected to the second information input of the switch, the inputs of the installation in 1 of the first and second triggers are connected respectively to the outputs of the third and fourth elements And the first and second groups in (Loo "- mation inputs of the converter are connected to the inputs and data of the second and third shift registers, the first and second groups of information inputs of the converter are connected respectively to the first and second groups of inputs of the code comparison circuit, the output of which is connected to the first input of the third element And the output of the second shift register connect not the input of the subtracted subtractor, the output of which is connected to the information input of the additional code generator, the resolution input of which is connected to the inverse output of the first trigger, the output of the third shift register is connected to the input I of the decremented subtractor and from the input of the first delay element, the first input of the fourth element And the connected  with the output of the EXCLUSIVE OR element, the first and second inputs of which are connected respectively to the first inputs of the first and second groups of information inputs of the converter, the second inputs of the third and fourth elements And are connected to the first output of the synchronization unit, the output of the second adder is connected to the input of the first term of the third adder, output which is connected to the second information input of the subtractor, characterized in that, in order to reduce hardware costs, it contains a third delay element, and One of the first element I is connected to the information input of the fourth shift register and with the input of the second term of the third adder, the outputs of the bits of the fourth shift register are connected to the information the inputs of the switch of the residual clocks system, whose output is connected to the input of the first addend of the second adder and through the third delay element to the input of the second addend of the second adder, the shift enable input of the fourth shift register is connected to the second output of the synchronization unit.