SU1116424A1 - Translator from residual class system code to position code - Google Patents

Abstract

SYSTEM CODE CONVERTER, WALKER RESIDUAL CLASSES INTO POSITION CODE containing control unit, first adder, first trigger, two AND elements, ШИИ element, and the direct output of the first trigger is connected to the control input of the adder, the control unit contains a clock pulse generator, and element I, and the output of the clock pulse generator is connected to the first input of the element I, the second input of which is connected to the forward trigger output, characterized in that, in order to increase speed, the converter contains three Shift register, multiplier, two adders, additional code driver, base switch, range switch, switch, AND cell, two delay elements, second trigger, control unit contains frequency divider, distributor, single pulse generator, second and third And elements, the first and second elements OR, the delay element, and the first element AND is connected to the information input of the frequency divider and to the first inputs of the second and third elements AND, the inverse output of the generator is new pulses connected to a clock input of a single pulse generator, the output of which is connected to a single trigger input, the second inputs of the second and third elements AND are connected respectively to the outputs of the first and second elements OR, the output of the frequency divider is connected to the input of the distributor and the input of the delay element, the first inputs of the first and the second element OR are connected to the output of the second bit of the distributor and myco, the outputs of the first and third bits of which are connected respectively to the second inputs of the first and second The OR elements, the pulse output of the three-pulse pulse distributor is connected to the zero trigger input, and in the converter the single inputs of the first and second triggers are connected respectively to the outputs of the first and second elements AND, the first input of the first and the first input of the second element AND are connected respectively to the outputs of the last and the first bits of the first shift register, the information input of which is connected to the output of the third element I, the first and second outputs of which are connected respectively to the first input the house of the OR element and the output of the second adder, the output of the multiplication unit is connected to the first input of the first adder, the output of which is connected to the first input of the third adder, the output of the first shift register is connected to

Description

the scraper input of the driver of the additional code, the output of which is connected to the first inputs of the second adder and the fourth element I, the output of which is connected to the first input of the multiplication unit, the second input of which is connected to the output of the base switch, the information input of the second shift register is connected to its output, with the second input of the second, the adder and the first input of the fifth element I, the output of which through the first delay element is connected to the second input of the first adder, the direct output of the first trigger is connected to the second the input of the OR element, which is connected to the control input of the additional code generator, the output of the third accumulator is connected to the information input of the third shift register, the data input inputs of which are connected to the outputs of the range switch, the forward output of the second trigger connected to the control input of the switch, the output of which is connected the second input of the third adder, the output of the third shift register is connected to the first input of the sixth element And to the first information input of the switch, the second informatonic input which is connected via the second zad.rzhki element with the output of the sixth And element, the second input of which is connected to the inverse output of the first trigger, the reset input of the additional code generator is connected to the second inputs of the first and second And elements and the code of the single pulse generator the first input of the element OR is connected to the code of the first bit of the distributor of the control unit, the inputs for controlling the input of the information of the first, second of the second and third shift registers is connected to the output of the single pulse generator of the control unit, the output of the second element, and which is connected to the shift control inputs of the first and second shift registers, the shift control input of the third shift register is connected to the output of the third control unit I, the output of the second distributor which is connected to the second inputs of the fourth and fifth elements And, the zero inputs of the first and second flip-flops are connected to the pulse output of the third bit of the distributor block at The inputs, the data inputs of the first and second shift registers are the first and second information inputs of the converter, the output of which is the data of the third shift diHCTpa.

The invention relates to computing, is intended to convert numbers from a system of residual classes to a position code, and can be used in digital automation and remote control systems.

The number converter is known, the contents of a bassy accumulator counter, a reference element, a binary number register, a modulo-sum counter, a bitwise comparison element, a code word residue receiving register, J5 multi-input element, And trigger

control and operation mode switch til.

A disadvantage of the known converter is low speed.

The closest in technical essence to the invention is a code converter of a system of residual classes into a position code containing a control block, an adder, a block of constants, n + 1 counters, a trigger, two AND elements and an OR element, and the installation inputs of the first n counters are converter inputs, their counting inputs are connected to the first input of the OR element and the first output of the control unit, the second output of which is connected by a single trigger input and the first control input of the adder, the second control input of which It is connected with the trigger output, the first input of the first element AND and the control input of Sp + 1) -th counter, the installation input of which is connected to the output of a block of constants, the input of which is connected to the output of the nth counter, the output of the device is connected to the output of the adder which is connected to the output of the OR element, the second input of which is connected to the counter input (htl) -ro of the counter and the output of the first element AND, the second input of which is connected to the third output of the control unit, the first and second inputs of which are connected to the Start input of the converter and the output the house of the second element And, the first and second inputs of which are connected to the outputs of the corresponding counters; in addition, the control unit contains a clock pulse generator, a trigger and an element And, the output of the clock generator is connected to the third output of the control unit and the first input element And, the second input of which is connected to the second output of the control unit and the output of the trigger unit and zero inputs of which are connected to the first and second inputs of the control unit, the first output of which is connected to the code of the element I This converter is also slow. The purpose of the invention is to increase the speed of interaction. The goal is achieved by the fact that the code converter of the system of residual classes into a position code containing a control unit, the first adder, the first trigger, the first and second AND elements, the OR element, and the direct output of the first trigger is connected to the control input of the adder, as well as the control unit containing clock generator, a trigger and an element I, and the output of the clock pulse generator connected to the first input of the element I, the second input of which is connected to the direct output of the trigger, contains the first, second and third shifts, multiplier, two adders, additional code generator, base switch, second trigger, range switch, switch, third, quarter, fifth and sixth And elements, first and second delay elements, and the control unit contains a frequency divider, a distributor, the generator of single pulses, the second and third elements AND, the first and second elements OR, the delay element, the output of the first element AND is connected to the information input of the frequency divider and the first inputs of the second and third elements AND, the inverse output of the clock pulse generator is connected to the clock input of a single pulse generator, the output of which is connected to a single trigger input, the second inputs of the second and third elements AND are connected respectively to the first path and the first and second I-SHI elements, the output of the frequency divider is connected to the input of the distributor and the input of the delay element, the first inputs of the first and second elements OR are connected to the output of the second discharge of the distributor and the pulses, the outputs of the first and third bits of which are connected respectively with the second inputs of the first and second elements OR, the pulse output of the third bit of the pulse distributor is connected to the zero input of the trigger, and in the converter the single inputs of the first and second triggers are connected, respectively, to the outputs of the first / and second elements AND the first input nepBoro and the first input of the second elements And connected respectively to the outputs of the last and first bits of the first shift register, the information input of which is connected to the output of the third element And, the first and second inputs of which are connected to Respectively with the first input of the OR element and the output of the second adder, the output of the multiplication unit is connected to the first input of the first adder, the output of which is connected to the first input of the third adder, the output of the first shift register is connected to the information input of the additional code generator, the output of which is connected to the first inputs of the second adder and the fourth element And, the output of which is connected to the first input of the multiplication unit, the second input of which is connected to the output of the base switch, the information input of the second p the shift horn is connected to its output, to the second input of the second adder and the first input of the fifth element I, the output of which through the first delay element is connected to the second input of the first adder, the direct output of the first trigger is connected to the second input of the RHH element, the output of which is connected to the control input of the shaper of the additional code, the output of the third adder is connected to the information input of the third shift register; the inputs of the input of which are connected to the outputs of the range switch, the direct output of the second trigger with dinene with the control input of the switch, the output of which is connected to the second input of the third adder, the output of the third shift register is connected to the first input of the sixth And element and to the first information input of the switch, the second information input of which is connected through the second delay element to the output of the sixth And element, the second input which is connected to the inverse output of the first trigger, the reset input of the driver additional code is connected to the second inputs of the first and second elements And the output of the delay element of the control unit For example, the start input of the single pulse generator is connected to the input of the converter start, the first input element OR is connected to the output of the first bit of the distributor of the control unit, the inputs of the first, second and third shift registers are connected to the output of the single pulse of the control unit, the output of the second element of which is connected to the shift control inputs of the first and second shift registers, the shift control input of the third shift register is connected to the output of the third The control unit, whose output of the second bit of the distributor is connected to the second inputs of the fourth and fifth elements And, the zero inputs of the first and second flip-flops are connected to the pulse output of the third bit of the distributor of the control unit, the input inputs of the first and second shift registers are first and the second information inputs of the transmitter, whose output is the output of the data of the third shift register. Fig. 1 shows a block diagram of the proposed converter; Fig. 2 shows the same control unit. The circuit (Fig. 1) contains a control unit 1, registers 2,3 and 4 shifts, adders 5,6 and 7, a multiplication unit 8, an additional code generator 9, a base switch 10, a range switch 11, a switch 12, triggers 13 and 14 , elements AND 15-20, element OR 21, and delay elements 22 and 23. The control unit (FIG. 2) contains a clock pulse generator 24, a frequency divider 25, a pulse distributor 26, a single pulse generator 27, an input 28, a trigger 29, elements AND 30-32, elements OR 33 and 34, a delay element 35, outputs 36 -42. The Converter code of the system of residual classes in the positional code works as follows. Using the switch 10, the binary code of the base P of the Residual classes system is set, the switch 11 sets the range of representation of numbers equal to, where P and P, j are the bases of the system of residual classes. The converter is started by a signal to the input 28 of the control unit 1. The trigger signal generator 27 single pulses produces a single pulse in the pause between the clock pulses of the generator 24 clock pulses. The output pulse of the single pulse generator 27 sets the trigger 29 to one state and is outputted from the output 36 of the control unit 1 to the control buses of the 2, 3 and 4 shift registers in which the source information is inputted in the form of parallel binary codes. Shift registers 2 and 3 contain n bits, and shift register 4 is Un 1. Bit. Parallel l – 1 bit binary codes of residuals σ (and the axis is read from the input buses of the converter and by the pulse 36 of the output 36 of control unit 1 are written to shift registers 2 and 3. A parallel 2n-2 bit binary code P / of the range of representation of numbers is read from switch 11 and written to shift register 4. Control unit .1 after setting the trigger 29 in one state produces the following on the outputs control sequences and Pulses. The clock pulses of the generator 24 clock pulses operating at a frequency f are divided by a frequency divider 25 times and are fed to the input of a three-bit pulse distributor 26. From the output signals of the pulse distributor 26, the elements OR 33 and 34 form two signals having a duration. n / i (. At the output of the element

OR 33, the logical unit signal is valid during the first 2 AND clock cycles of the number converter, and the output of the OR 34 element is set to a logical unit signal after 1 clock cycle after the number converter starts up and is valid for the next 2 N cycles until the end of the conversion cycle. OR 33 and 34 control elements AND 31 and 32, respectively, through which the clock pulses of the generator 24 clock pulses arrive at the fourth 37 and third 38 output of the control unit 1. Thus, at the output 37 of the control unit 1 no valid sequence of clock pulses during the first 2 cycles of operation of the transducer and numbers, and the third outlet 38 - after n cycles vfabatyvaets sequence of clock pulses for the next 2 cycles and.

The output pulses of the frequency divider 25 are delayed by the delay element 35 for the duration of the clock pulse of the generator 24 clock pulses and arrive at the second 39 output of control unit 1, the first 40 and sixth 41 outputs of which act5.

signals of the first and second bits of the pulse distributor 26, respectively.

The signal from the code of the AO control unit 1 enters through the element IL 21 55 to the control input of the additional code generator 9 and translates it into the formation mode

my or additional difference code (residuals / I - (). If the residual difference is odd, then the output of the first bit of shift register 2 is a logical unit signal. If the residual difference is even, then the output of the first bit of shift register 2 is a logical zero signal. Direct or additional residual difference code gives the output of the M-th bit of register 2 shift

zero

logical signal

or one Nitsi respectively.

After the clock runs, after starting the allocator, at output 39 of control unit 1, an impulse is accumulated, in which the shaper 9 of the additional code is reset to the initial state, as well as the information of the first and fifth digits of the shift register 2, is rewritten through elements 16 and 15 in triggers 13 and 14 respectively. Thus, the trigger 13 contains information about the evenness or oddness of the difference of residuals, and the trigger 14 contains information about the sign of the difference of residuals.

In the second and clock cycles the binary code of the residual difference is shifted under

the course 37 of the control unit 1 through the additional code generator 9 and the element. AND 18 to the first input of the block B multiplication.

The shaper 9 of the additional code converts the additional code of the residual difference into the direct code if its input is controlled via the code. Under the action of a series of clock pulses from the output 37 of the control unit 1, the binary codes of the residuals of C and shifted, starting with the least significant bit, from the outputs of the registers 2 and 3 of the shift, respectively. The shaper 9 of the additional code converts the binary code of the remainder of the C into the additional code, which is fed to the first input of the sum of the device 5. The sequential binary code formed by the adders 5 from the additional code of the residual k and the direct code of the residual N. , shifted from the output of the shift register 3, is written through the element 17 to the shift register 2 during the clock cycles. Thus, after the clock runs, the converter in shift register 2 is set. By the action of clock pulses from the element OR 21 a signal is received from the logical unit of the direct output of the trigger 14 or it passes without changing the direct code of the residual difference when the trigger 14 is in the zero condition.

Consequently, at the output of the additional code generator 9 during the second P cycles, a direct code of the absolute value of the residual difference is generated, which, through the AND 18 element, begins, starting with the least significant bit, to the serial input of the multiplication unit 8. In the latter, a sequential binary code of the product P -o is generated (I starting with go and (of the least bit).

The adder 7 is set to the summing mode, if the trigger 14 is set to one state (the sign of the residual difference is negative), or in the subtractor condition, when the trigger 14 is in the zero state (the sign of the residual difference is positive). Depending on the mode of operation, the adder 7 generates a serial binary code of magnitude 1 cC i P:, .- / о

The serial binary code of the remainder is shifted during the second and clock cycles, starting with the flush bit, under the action of the clock pulses from the output 37 of the control unit 1 from the output of the shift register 3 and enters through the element 19 and the element

22 delays per clock to the input of adder 7. Delay element 22 shifts by one bit the consecutive binary code of the remainder o6 with respect to the serial binary product code, i.e. implements the operation of multiplying the binary code of the remainder by two.

Switch 12 connects the output of register 4 to the input of adder 6- if trigger 13 is in one state (the odd difference), or connects the input of adder 6 to the output of clock delay element 23 when trigger 13 is in zero state (residual difference even) Element AND 20 blocks the input of delay element 23 if trigger 14 is in the single state (the sign of the residual difference is negative), or connects the output of shift register 4 to the input of element

23 delays when trigger 14 is in the zero state (the sign of the residual difference is positive).

After p clocks after starting the converter, the binary code of the P P value is shifted under the action of the clock pulses of the third output of the control unit 1 from the shift register 4, and starting from the least significant bit, comes through the switch 12 to the input of the adder 6 when the residual difference is odd.

In this case, at the output of the adder 6, a serial binary code is generated, the magnitude of the value of P Pfj -t 2oL t P C. -I)

which is equal to twice the converted number. When the residual difference is even and the sign of the residual difference is positive, then the binary HbDi code P P (2 is shifted from register

ra 4 shift through the element and 20,

the delay element 23 per clock and the switch 12 to the input of the adder 6. The delay 23 element per cycle provides a shift by one bit of the serial binary code of the value of P with respect to the serial binary code generated at the output of the adder 7, i.e. implements the multiplication operation by two. In that

In the case of the output of the adder 6, a serial binary code of value 1 1.cl iL-dJi is formed which is equal to twice the value of the transformed number.

In that case, if the residual difference is even and the sign of the residual difference is negative, then element 20 is closed by a signal from the inverse output of the trigger 14, and at the output of the switch

12 binary zero is valid. At the output of the adder 6, in this case, the binary code of the value 2d is generated. p ,, which is equal to twice the value of the converted

numbers

The serial binary code of the converted number from the output of the adder 6 is written, starting with the least significant bit, into register 4

shift under the action of torque pulses from the third 38 output of the control unit 1. After 3 n cycles after starting the number converter at the pulse output of the third bit

a pulse distributor 26, a pulse is formed, resetting the trigger 29 of the control unit 1 to the zero state, in which the AND 30 element is blocked. At the same time, this impulse arrives at the seventh 42 output of the control unit 1 and resets the triggers 13 and 14 to the 1-state. The number conversion loop ends, and in shift register 4, the binary code of the converted number is fixed. The shift register 4 shift is selected so that the lower bit of the binary code of the transformed number (the second bit of the double value of the transformed number) at the end of the conversion cycle is not in the first bit of the shift register 4.

X

ff

.-3LJp f., / G

rw

 DD I 1

Thus, with the same representation ranges of numbers, the proposed converter is approximately 3 times as fast as the prototype, and with mallow values of the representation range with an increase in the representation range, the performance gain of the proposed device over the prototype increases. In addition, the conversion time in the pre-prepared is constant and does not depend on the choice of the bases of the net of residual classes and the numbers to be transformed.

Mfnf

36 37

39 l

Claims (1)

A RESIDUAL CLASS SYSTEM CONVERTER IN A POSITION CODE, comprising a control unit, a first adder, a first trigger, two AND elements, an OR element, the direct output of the first trigger being connected to a control input of the adder, the control unit contains a clock pulse generator, a trigger and an AND element, the output of the clock generator is connected to the first input of the And element, the second input of which is connected to the direct output of the trigger, characterized in that, in order to improve performance, the converter contains three registers shift unit, multiplication unit, two adders, additional code generator, base switch, range switch, switch, four AND elements, two delay elements, a second trigger, the control unit contains a frequency divider, distributor, single pulse generator, second and third AND elements, the first and the second OR element, the delay element, wherein the output of the first AND element is connected to the information input of the frequency divider and to the first inputs of the second and third AND elements, the inverse output of the clock in connected to the clock input of a single pulse generator, the output of which is connected to a single trigger input, the second inputs of the second and third elements AND are connected respectively to the outputs of the first and second elements OR, the output of the frequency divider is connected to the input of the distributor and the input of the delay element, the first inputs of the first and the second OR elements are connected to the output of the second discharge of the pulse distributor, the outputs of the first and third bits of which are connected respectively to the second inputs of the first and second OR elements, and the pulse output of the third category of the pulse distributor is connected to the zero input of the trigger, and in the converter the unit inputs of the first and second triggers are connected respectively to the outputs of the first and second elements AND, the first input of the first and first input of the second elements And are connected respectively. with the outputs of the last and first bits of the first shift register, the information input of which is connected to the output of the third AND element, the first and second outputs of which are connected respectively to the first input of the OR element and the output of the second adder, the output of the multiplication unit is connected to the first input of the first adder, the output of which is connected the first input of the third adder, the output of the first shift register is connected to inforSU _t, 1116424 mation additional dome tional input of the code whose output is connected to the first inputs of the second sums ator and the fourth element And, whose output is connected to the first input of the multiplication unit, the second input of which is connected to the output of the base switch, the information input of the second shift register is connected to its output, with the second input of the second adder and the first input of the fifth element And, the output of which is through the first delay element is connected to the second input of the first adder, the direct output of the first trigger is connected to the second input of the OR element, the output of which is connected to the control input of the additional code generator, the output is the third adder is connected to the information input of the third shift register, the data input of which is connected to the outputs of the range switch, the direct output of the second trigger is connected to the control input of the switch, the output of which is connected to the second input of the third adder, the output of the third shift register is connected to the first input of the sixth element And with the first information input of the switch, the second information input of which is connected through the second delay element with the output of the sixth element And, the second input of which is connected with the inverse output of the first trigger, the reset input of the additional code generator is connected to the second inputs of the first and second elements AND and the output of the delay element of the control unit, the start input of the single pulse generator of which is connected to the input of the converter Start the first input of the OR element is connected to the output of the first discharge of the block distributor controls, inputs for controlling the entry of information first,. the second and third shift registers are connected to the output of the single pulse generator of the control unit, the output of the second element And which is connected to the inputs of the shift control of the first and second shift registers, the input of the shift control of the third shift register is connected to the output of the third element And of the control unit, the output of the second discharge of the distributor which connected to the second inputs of the fourth and fifth elements AND, the zero inputs of the first and second triggers are connected to the pulse output of the third discharge of the distributor and control inputs of the input data of the first and second shift registers are the first and second data inputs of the converter, the output of which is you | sod third data shift PE _(cittern.