SU1180885A1 - Square-law function generator - Google Patents

Abstract

1. SQUARE, containing three delay elements, three OR elements, three AND elements, characterized in that, in order to expand the field of application due to the possibility of working with numbers presented both in digital and analog form, the first and second shift registers, adder. Trigger, switch, first and second pulse clock, synchronization unit, two pulse drivers, output of the first shift register connected to the first input of the adder, the output of which is connected to the information input of the first, shift register, the synchronization input of which is connected to the synchronization input of the second shift register and the first the output of the synchronization unit, the second output of which is connected to the control inputs of the first and second shift registers, whose information inputs are connected to the zero bus of devices a, the output of the second shift register is connected to the inverse reset input of the trigger and to the first input of the first OR element, in opoii, the input of which is connected through the first delay element to the direct output of the trigger, the information input of the second shift register is connected to the output of the first And element, the first and the second inputs of which are connected respectively to the output of the first OR element and to the inverse output of the trigger, the information input of which is connected to the first output, the first pulse clock, the second output of which is connected to the first one The second element is And, the output of which is connected to the second input of the adder, and the second input is connected to the output of the switch, the control input of which is connected to the output (L of the second clock pulse, whose information input is connected to the information input of the first clock and the third output of the block in synchronization, the fourth output of which is connected to the first input of the third OR element, the second input of which 00 through the second delay element is connected to the output of the second shift register, the output of the third OR element (X connect The fifth output of the synchronization unit is connected to the start input of the first and second pulse drivers, whose information inputs are information inputs of the device, the output of the first pulse driver is connected to with the first input of the second element OR, the output of which is connected to the control input of the first clock and with the first input of the third element AND, whose output

Description

connected to the control input of the second clock, and the second input to the second input of the second OR element and the output of the second pulse driver.

2. The quadrator according to claim 1, wherein the synchronization unit comprises a pulse generator, a pulse distributor, a generator of identical pulses, a trigger, two switches, a NOT element, the output of the pulse generator is connected to the first output of the synchronization unit and the distributor input pulses, the first output of which is connected to the fourth output of the synchronization unit, and the second output is connected to the third output of the synchronization unit, the information input of the trigger and the information input of the single pulse generator, the control input coupled to an output of the first switch, the first input of which is connected to an earth bus, and the second input via NOT element is connected to an earth bus, the output generator

connected to the input of the second switch, the first output of which is connected to the control input of a trigger, the direct output of which is connected to the second output of the synchronization unit, the second i output of the second switchboard connected to the fifth output of the synchronization unit.

3. The quadrator according to claim 1, said that the clock contains two NOT elements, the OR element and two NAND elements, the first input of the first NAND element is connected to the information input of the tachometer and the first input of the OR element, output which is connected to the first input of the second NAND element, the output of which is connected to the second output of the clock and the second input of the first NAND element, the output of which through the first element is NOT connected to the first output of the clock and the second input of the second element NAND controlling clock input via second element T does not - with the second input of the OR element.

one

The invention relates to automation and computer technology and is intended to be squared or to form the sum of squares of two quantities represented in digital or analog form of information representation.

The purpose of the invention is to expand the scope of use due to the possibility of working with numbers presented in both digital and analog form.

FIG. 1 shows a structural scheme of the proposed quad; in fig. 2 is a block diagram of a synchronization unit and pulse clock.

The quadrator (figure 1) contains the registers 1 and 2 of the shift, the adder 3, the trigger 4, the elements OR 5-7, the elements And 810, the elements 11-13 delay per clock, the switch 14, the block 15 synchronization clocks 16 and 17 pulses, drivers 18 and 19 pulses, information inputs 20 and 21 devices.

The block (FIG. 2) contains a trigger 22, a pulse generator 23, a pulse distributor 24, a single-pulse generator 25, switches 26 and 2 HE element 28, output buses 29-33.

The tactile 16 or 17 pulses (Fig. 2) contains two elements AND-NOT 34 and 35, two elements NOT 36 and 37, element OR 38, two inputs 31 and 39, two outputs 40 and 41.

Quad works as follows.

In the initial state, the switch 27 of the synchronization unit 15 connects the output of the generator 25 single pulses to the information input of the trigger 22. The generator 23 of the pulses of the synchronization unit 15 generates a sequence of clock pulses, of which n-bit distributor 24 pulses form n sequences of pulses of duration 1 / f , period T Tni / f and shifted relative to each other by time f 1 / f, where f is the frequency of the clock pulses of the generator 23, n is the number of bits of the registers 1 and 2 of the shift. Switch 26. Gives 1: Ignition logic 1 from the output of the element NE 28 to the start input of the generator 25 single pulses, on which code a single pulse is emitted from the sequence of the th digit of the distributor 24 pulses The output pulse of the generator 25 single pulses through the switch 27 is fed to information input trigger 22, set it to a single state. The logical 1 signal of the direct output of the trigger 22 is fed to the control inputs of the shift registers 1 and 2, which, under the action of the clock pulses from the first output of the synchronization unit 15, are set to the zero state, since the logical O signal acts on their data input. The trigger 4 is set to the zero state by a zero signal shifted from: the output of the shift register 2. Thus, in the initial state, the shift registers 1 and 2, as well as the trigger 4, are in the zero state. In the initial state with a zero signal at the control input switch 14 connects the output of the element OR 7 to the second input of the element AND 9. The calculation mode is set by switch 27 by connecting the output of the generator 25 single pulses to the start inputs of the drivers 18 and 19 pulses. The calculations in the quad start after starting with the switch 26 of the generator 25 single pulses, the output pulse of which triggers the pulse former 18 and 19. At the outputs of the formers 18 and 19 pulses, pulses are formed, the duration of which is proportional to the signals (analog or digital) acting on the information inputs 20 and 21 of the device. If the duration of each pulse-50 owl shaper 18 and 19 pulses is different, then the longest pulse is allocated at the output of the SHSh 6 element, and the shorter pulse is at the output of the AND 10 element, under the action of which the clock pulse 17 forms About the 55th 54th distributor bit of 24 pulses is a strobe of a burst of pulses, the number of which is proportional to the smallest value acting on one of the information inputs of 20 or 21 devices. The pulse strobe 17 switches the switch 14 to a state in which the output of the delay element 13 is connected to the second input of the element AND 9. Under the action of the maximum output pulse of the element OR 6 and the pulse order of the first distributor pulse 24, the pulse 16 forms the first pulse the output of the strobe is a burst of pulses, and at the second output a burst of pulses, the number of which is proportional to the largest value acting on one of the information inputs of 20 or 21 devices. The strobe of the first clock pulse output 16 opens element I 9, and the pulse burst of the second clock output 16 pulse arrives at the information input of trigger 4. The first pulse of the packet sets trigger one 4 in the nth cycle (corresponding to the shift of code bits from the register outputs) I and 2 shift). Setting trigger 4 to a single state results in the formation of a zero signal at its inverse output, blocking the element 8, and at the direct output, a single signal which, after the delay time of the element I1, lags per cycle through the element OR 5 at the first input of the element AND 8. Under the action of the clock pulses of the first output of the synchronization unit 15 from the output of the shift register 2 in the first cycle, the lower bit of the initial zero code is shifted, the signal of which is fed to the inverse reset input of the trigger 4 and set it is in zero position. In the zero state at the inverse output of the trigger 4, a single signal is generated, which removes the blocking of the element AND 8. Due to the delay for the clock by the element 11 of the signal of the direct output of the trigger 4, the pulse signal is generated at the output of the element 8, which is recorded in the first cycle as a lower order Yes, the code in the register 2 shift under the action of the clock pulses of the first output of the synchronization unit 15. During the first clock cycle, the output signal of the first bit distributes л 24 pulses acting on the fourth output of the synchronization unit 15 through the OR 7 element to the input of the delay element 13. In the next cycle, the output signal of the element 13 delay through the switch 14, the element And 9, the adder 3 is fed to the information input of the register 1 shift. Under the action of the clock pulses of the first output of the synchronization unit 15 in the second clock, a single signal is recorded in the shift register 1 as the second code bit. During the subsequent cycles from the second to the nth, the bits of the codes from the first to the nth under the action of T iKTOBbK of the pulses of the first output of the synchronization unit 15 are shifted by the output of the shift registers 1 and 2. Thus, after the first calculation step, the binary codes of the square function 2 x 2 and the argument X | are generated in the shift registers 1 and 2, respectively. one . At the second and subsequent computation steps, before the end of the smallest pulse signal at the outputs of the pulse formers 18 and 19, the device generates in the shift registers 1 and 2, respectively, the binary codes of the quadratic function and the argument according to the ratio 2., + 4 x ,,. + 2, (1 where x and i are the values of the argument of a quadratic function on i and i – 1 extraction steps, respectively. For example, setting trigger 4 to one state by the i-th pulse of a packet acting on the second clock of the 16 clock pulse, provides the formation of in registers 1 and 2, the shift of binary codes of values 2 X; and x-, respectively, according to relation (1), as follows: Under the action of the clock pulses of the first output of synchronization unit 15, the binary code of value 2 X is shifted to the first input of adder 3; .. quadratic functions in the previous compute step And from the output of the register 2 shift through the elements 12 and 13 of the delay per clock, the elements OR 7, AND 9, and the switch 14 to the second input of the adder 3 shifts the binary code of the argument 4 x Sequential delay by elements 12 and 13 of the delay by two clocks provides a shift by two bits of the binary code of the argument in the previous step of calculating with respect to the binary code of the 2 x function shifted from the output of the shift register 1. The adder 3 generates, according to relation (1), the binary code of the 2 x quadratic function at the i-th calculation step, which is sequentially nach In the lower order bit, it shifts from the output of the adder 3 to the shift register 1. The signal of the two units of the best bit is supplied from the fourth output of the synchronization unit 15 through the elements OR 7, AND 9, the delay element I3 and the switch 4 to the second input of the adder 3. At this time, in register 2, the binary code of the value x;., Is incremented by one. Indeed, setting trigger 4 to one state ensures the breaking of the circuit of circulation of codes from the output of shift register 2 to its input, since element 8 is closed by the zero signal of the inverse output of trigger 4. Therefore, before trigger 4 returns to the zero state For the shift register code 2, zero signals are recorded. The trigger 4 returns to the first zero state, starting with the lower bit, the zero code signal, which is shifted from the output of the shift register 2. The transition of the trigger 4 from the single state to the zero state results in the formation at the output of the element And 8 of a pulse signal, due to the delay by the element 11 of the delay of the single signal of the direct output of the trigger 4 of its previous state. Consequently, instead of a zero signal shifted from the output of register 2, a single signal from the output of element I B arrives at the information input of the shift register 2. The remaining bits of the binary code shifted from the output of shift register 2 are rewritten into shift register 2 without changing through the elements OR 5 And I, B, so for 7 the trigger 4 is in the zero state. Thus, the binary code in the register 2 of the shift at each step of the calculations is increased by one and corresponds to the number of pulses acting on the second clock output 16 Pulse. After the lowest pulse has expired, the element And 10 is closed at the output of the driver 18 or 19 of the pulses, and the zero signal is set at the output of the clock 17. The zero signal of the first output and clock pulse 17 provides for the switch 14 to return to its initial state, in which the output of the element OR 7 is connected to the second input of the element AND 9, at the first input of which the gate pulse output 16 of the pulses continues to operate until the end of the maximum pulse on The output is 18 or 19 pulses. In the time interval from the moment of ending the smallest to the moment of termination of the largest pulse at the outputs of the formers 18 and 19 pulses, the device forms the sum of squares of two quantities according to the following relation y – t, + x (y + x) + 2y + 1 where X is the smallest input value; y is the largest input value. By the moment of the end of the smallest pulse (corresponding to the smallest input value) in shift register 1, a binary code of 2 times the smallest square of the smallest value is formed according to (1) and a duplicate code X of the smallest value in shift register 2. Suppose that the smallest impulse of magnitude X ends at the i-th step of the computation, then and. Therefore, after the i-ro step of the calculations, the shift register 1 contains the binary code of the value 2x y, + x, and the shift register 2, the binary code of the value y-, which is doubled with delay 12. On the element OR 7, a sequential binary code of the value 2 y + 1 is formed, since the single signal of the fourth output of the synchronization unit 15,858 is written to the low-order bit of the code. The serial dbichny code of the value 2 y, - + 1 is fed from the output of the element OR 7 through the switch 14 and the element AND 9 to the second input of the adder 3, to the first input of which from the output of the shift register 1 the sequential binary code of the value y + x is shifted. The result of the summation, which according to relation (2) is equal to the value of y, + x, is written, starting with the least significant bit, into the shift register 1 under the action of the clock pulses of the first output of the synchronization unit 15. At the same time, at the (i + 1) -th computation step during n cycles, the binary code in shift register 2 in the rewriting process from output to input through the elements OR 5 and AND 8 is incremented by one as previously described. In all subsequent steps, the calculations are performed in a similar manner until the moment of termination of the largest impulse of the input quantity, y. In this case, at the output of the element OR 6, a zero signal is set, which sets the first and second outputs of the clock of the 16 pulses to zero signals. The zero signal of the first clock pulse output 15 blocks the element AND 9. In the shift register 1 in a dynamic way by circulating the binary code through the adder 3, the sum of squares of the two input values y + in the shift register 2 is stored dynamically by circling the code through the elements OR 5 And AND 8 is the binary code of the largest input variable y. The clock 16 or 17 pulses works as follows. A sequence of pulses is fed to input 31, and a control signal to input 39. In the case of absence of control signals at input 39, at the output of the HE 36 element, a signal of the optical 1 is received, arriving through the LI-38 element at one of the AND-34 element inputs. During the pause between the pulses at the input 31 at the output of the NAND element 35, a logical 1 signal is generated, which conscientiously with a single output signal of the element OR 38 sets the output of the NAND 34 element to a logical O signal, blocking the NAND 35 element during the pulse of input 31. The 1 output signal of the NAND 35 element supports the logical output signal lementa NOT 37.

Acting a single signal at control input 29 at the output of the NOT element 36, a logical O signal is established. During the pause between the pulses at the input 31 at the output of the OR 38 signal, a logical 0 signal is formed, which forms the single strobe signal at the output of the IS-HE 34 passes a sequence of pulses of input 31 through the elements AND-NOT 35 and NOT 37 to the output of the clock pulse impulse8510

owls In this mode, during a pulse at input 31, a zero signal at the output of the AND-HE element 35 blocks the AND-HE element 34, at the output of which the logical 1 strobe signal is maintained.

Thus, the proposed quad can be used in

the formation of a quadratic function, if an input signal (analog or digital) is received at one of the inputs 20 or 21 of the device, and another at the other information input of the device

the zero signal is valid. If the signals at inputs 20 and 21 of the quadrant act simultaneously, then the quadrator forms the binary code of the sum of the squares of the two input values.

Claims (3)

1. SQUARE containing three delay elements ”three OR elements, three AND elements, characterized in that, in order to expand the scope due to the ability to work with numbers presented in both digital and analog form, the first and second shift registers, adder, trigger, switch, first and second pulse clocks, synchronization unit, two pulse shapers, the output of the first shift register is connected to the first input of the adder, the output of which is connected to the information input of the first, shift a histra, the synchronization input of which is connected to the synchronization input of the second shift register and the first output of the synchronization block, the second output of which is connected to the control inputs of the first and second shift registers, the information inputs of which are connected to the zero bus of the device, the output of the second shift register is connected to the inverse trigger reset input and with the first input of the first OR element, the second input of which is connected through the first delay element to <direct trigger output, the information input of the second shift register is connected nen with the output of the first AND element, the first and second inputs of which are connected respectively to the output of the first OR element and with the inverse trigger output, the information input of which is connected to the first output of the first pulse clock, the second output of which is connected to the first input of the second And element, the output of which is connected to the second input of the adder, and the second input is connected to the output of the switch, the control input of which is connected to the output of the second clock pulse, the information input of which is connected to the information input m of the first clock and the third output of the synchronization unit, the fourth output of which is connected to the first input of the third OR element, the second input of which through the second delay element is connected to the output of the second * shift register, the output of the third OR element is connected to the second information input of the switch and through the third element? delays - with the first information input of the switch, the fifth output of the synchronization unit is connected to the start input of the first and second pulse shapers, the information inputs of which are information inputs of the device, the output of the first pulse shaper is connected to the first input of the second OR element, the output of which is connected to the control input of the first a clock and with the first input of the third element And, the output of which SU „ _U 1180885 is connected to the control input of the second clock, and the second input is connected to the second input of the second OR element and the output of the second pulse shaper. 2. The quadrator according to claim 1, wherein the synchronization unit comprises a pulse generator, a pulse distributor, an identical pulse generator, a trigger, two switches, an element NOT, the output of the pulse generator is connected to the first output of the synchronization unit and the input pulse distributor, the first output of which is connected to the fourth output of the synchronization unit, and the second output is connected to the third output of the synchronization unit, the information input of the trigger and the information input of the single pulse generator, the control input to of which is connected to the output of the first switch, the first input of which is connected to the ground bus, and the second input through the element is NOT connected to the ground bus, the output of the generator is connected to the input of the second switch, the first output of which is connected to the control input of the trigger, the direct output of which is connected to the second the output of the synchronization unit, the second 'output of the second switch is connected to the fifth output of the synchronization unit. 3. The quadrator according to claim 1, characterized in that the clock contains two NOT elements, an OR element and two AND elements, the first input of the first AND element NOT connected to the information input of the clock and the first input of the OR element, output which is connected to the first input of the second AND-NOT element, the output of which is connected to the second output of the clock and the second input of the first AND-NOT element, whose output through the first element is NOT connected to the first output of the clock and to the second input of the second AND-NOT element, control input of the clock through the second element T does not - with the second input of the OR. I