SU1077539A1 - Multichannel device for forming pulse trains - Google Patents

Abstract

1. MULTI-CHANNEL DEVICE FOR FORMING PULSE SEQUENCES, containing a reference quartz frequency generator, programmed 1 "1st frequency divider, the output of which is connected to the first input of the pulse counter, the first input of the programmable frequency divider is connected to the first input of the operational memory device, the first output of which is connected to the programmable frequency divider connected to the first input of the operational memory device, the first output of which is connected to the programmable frequency divider. the input of the adder, the output of which through the first register is connected to its second input and to the first input of the second register, the output of which is connected to the first in the controlled delay line, the output of which is connected to the second input of the second register, the second input of the controlled delay line is connected directly to the first inputs of the first and second AND-NOT elements and through a counting trigger with the second inputs of the first and second AND-NOT elements, as well as the formation channels, the first input of each of which is connected to the output of the first NAND element, the second input of each channel of the formation is connected to the first input of the random access memory, the third input of each channel of the formation of the connection It is not provided with a second RAM input, characterized in that, in order to speed up the operation and improve the accuracy of the device, a key, a control unit and a D-flip-flop are entered into it, with the output of the second AND-NOT element connected to the fourth input of each. the formation channel, the first input, the B-flip-flop is connected to the first input and the pulse counter at the input of each formation channel, and the second input is connected to the output of the pulse counter, the first output, V D-flip-flop, is connected to the second input of the first register and with the input of the counting trigger, the second output of the D-trigger is connected to the second input L of the pulse counter, the third input of which is connected to the output of the control unit, the first input of which is connected to the second output of the operational memory, the second I input of the control unit connected to the output, the adder and the first input switch connected to the output of the generator poles hydrochloric quartz frequency switch output is connected to the second input of the programmable frequency divider, the second input of which is connected to the second input key, the second register output is connected to a sixth input of each forming channel. 2. The multichannel device for forming pulse sequences according to claim 1, characterized in that each channel of formation consists of two pulse shapers, the outputs of which are connected to the trigger inputs, and each pulse shaper contains an adder, the output of which is under

Description

keys to the first inputs of the first and second D-flip-flops, the first output of the random access memory is connected to the first input of the adder, the second output of the operational memory is connected to the first inputs of the first and second pulse counters, the second inputs of which are combined, the outputs of the first and second pulse counters respectively i Stekno is connected to the first inputs of the third and fourth D-flip-flops and the first and second elements of the NL-NOT, the second inputs of the third and fourth D-flip-flops are combined and connected to the second inputs pulse counters and to the first inputs of the fifth and sixth D-flip-flops, the second inputs of which are respectively connected to the outputs of the first and third elements OR-NOT and the second and fourth elements SH-NOT, the second input of the first element OR-NOT connected to the first output of the first D -trigger, the second output of which is connected to the first input. the third element OR NOT, the second input of which is connected to the output of the second .D-flip-flop, the output of the fourth D-flip-flop is connected to the first input of the fourth element SH-NOT, the second input of which is connected to the first output of the second D-flip-flop, the second output of which is connected to the second

the input of the second element OR NOT; the second input of the first D-flip-flop is connected to the third input of the first pulse counter, to the first input of the shaping channel and to the first input of the first register, the second input of which is connected to the second output of the adder and the first input of the second register, outputs which are connected to the first inputs of the multiplexer, the second inputs of which are connected to the outputs of the first register, the third input of the multiplexer is connected to the outputs of the fifth and sixth D-flip-flops and the first input of the controlled delay line, the second one connected to the multiplexer output, the output of the controlled delay line is the output of this driver, the second input of the second register is connected to the second input of the second D-flip-flop, to the third input of the second pulse counter, and to the fourth input of the formation channel, the first input of the operational memory the device is the second input of the formation channel, the second input is the third input of the formation channel, the second input of the adder is the sixth input of the formation channel, and the second inputs of the counters pulses are the fifth input of the channel formation.

The invention relates to a pulse technique and can be used to control the time intervals of test and synchronization sequences of signals in automated complexes of functional and parametric control of BIS random access memory devices (RAM) and BIS microprocessors, as well as a system for synchronizing high-speed computers,

A multichannel device for generating pulse sequences is known, comprising a pulse generator, a shaping device and n shaping channels.

The disadvantage of this device is that the pulse generator

operates in the start-stop mode, therefore, as a pulse generator, highly stable and accurate reference frequency oscillators with quartz stabilization operating in continuous mode cannot be used. This significantly reduces the accuracy of the formation of time intervals. Delay task range

10 and the duration of the synchronization pulses in this device can not be longer than their period. In addition, there is no possibility; control of the following period,

15 by the delay and duration of the synchronization pulses at their frequency (in real time),

which reduces the possibility of functional control BIS.

The closest technical solution to this invention is a device for generating pulse sequences, comprising a quartz frequency generator, a software frequency divider connected to a pulse counter, two clock frequency phase generator units, two clock frequency phase selectors, and the serially connected first and second registers , the first and second adders, the first pulse counter, the first controlled delay line, the first RAM, the counting trigger, the outputs of which are connected to the first mi and the second elements of the NAND and n formation channels.

The disadvantage of this device is the limited speed due to the fact that the need to select a new phase of the clock frequency at the beginning of each cycle of formation of time intervals leads to the prohibition of the clock frequency at the end of each cycle for several periods of synchronization pulses.

In addition, the error associated with the selective choice of phase clock frequency, reduces the accuracy of the formation of the delay and the duration of the synchronization pulses.

The components of this error are:

the error in the relative position of the phases at the outputs of the block forming the phase set of clock frequencies;

the error due to the difference in the propagation delays of signals from different inputs of each clock frequency selector to its outputJ

the error due to the difference in the intrinsic delays in signal propagation through the first and second clock phase selectors.

The aim of the invention is to increase the speed and increase the accuracy of the device.

This goal is achieved by the fact that a multichannel device for generating pulse sequences containing a generator. a reference quartz frequency, a programmable frequency divider, the output of which 55 strokes are connected to the inputs of the rigo is connected to the first input of the counting trigger, and each pulse pulse generator, the first input of the programmable pulses contains an adder, the outputable frequency divider is connected. with the first input of a random access memory, the first output of which is connected to the first input of the adder, the output of which through the first register is connected to its second input and to the first input of the second register, the output of which is connected to the first input of the controlled delay line, the output of which is connected to the second input the second register, the second input of the controlled delay line is connected directly to the first inputs of the first and second AND-NOT elements and through a counting trigger with the second inputs of the first and second AND-NOT elements, as well as the formation channels, the first input of each of which is connected to the output of the first IS-evil, the second input of each formation channel is connected to the first input of the random access memory, the third input of each formation channel is connected to the second input of the operational memory, the key is entered block control and D-flip-flop, the output of the second AND-NOT element is connected to the fourth input of each formation channel, the first input of the B flip-flop is connected to the first input of the pulse counter and to the fifth input of each formation channel, and the second input is connected to the output of the pulse counter owls, the first release of the D-flip-flop; with the second input of the first register and with the input of the counting trigger, the second output of the D-trigger is connected to the second input of the pulse counter, the third input of which is connected to the output of the control unit, the first input of which is connected to the second output of the random access memory, the second input of the control unit connected to the output of the adder, and the first input of the key is connected to the output 5 of the quartz frequency generator, the output of the key is connected to the second input of the programmable frequency divider, the second input of which is connected to the second key entry, and; the output of the second register is connected to the sixth input of each channel of the formation, as well as the fact that each channel of the formation in it consists of two pulse shapers that are connected to the first inputs of the first and second D-flip-flops, the first input of the random access memory is connected to the first input of the memory, the second output of the operational memory is connected to the first inputs of the first and second pulse counters, the second inputs of which are combined, the outputs of the first and second pulse counters, respectively, The first inputs of the third and fourth D-flip-flops and the first and second elements OR-NOT are the second inputs of the third and fourth D-flip-flops combined and connected to the second inputs of pulse counters and to the first inputs of the fifth and sixth D-flip-flops, the second inputs of which respectively, are connected to the outputs of the first and third elements OR NOT and the second and fourth elements OR NOT, the second input of the first element OR NOT is connected to the first output of the first D-flip-flop, the output of which is connected to the first input of the third element OR NOT, the second input koto The second is connected to the output of the second D-flip-flop, the output of the fourth D-flip-flop is connected to the first input of the fourth OR-NOT element, the second input of which is connected to the first output of the second D-flip-flop, the second output of which is connected to the second input of the second OR-HY element, the second input of the first D-flip-flop is connected to the third input of the first counter, to the first input of the formation channels and to the first input of the first register, the second input of which is connected to the second output of the adder and to the first input of the second register, the outputs of which are connected to the first inputs of the multiplexer, the second inputs of which are connected to the outputs of the first register, the third input of the multiplexer is connected to the outputs of the fifth and sixth trigger and the first input of the controlled delay line, the second input of which is connected to the output of the multiplexer, the output of the controlled delay line is the output of this pulse generator, the second input of the second register is connected to the second input of the second D-flip-flop, to the third input of the second pulse counter and to the fourth input of the forming channel, the first operational input the storage device is the second input of the formation channel, the second input is the third input of the formation channel, the second input of the adder is the sixth input of the formation channel, and the second inputs of the pulse counters are the fifth input of the formation channel. The drawing shows a functional diagram of a multi-channel device dp forming pulse sequences. The device contains a generator 1 reference quartz frequency, a software divider 2 frequencies, a pulse counter 3, an adder 4, a random access memory (RAM) 5, registers 6.7, a controllable delay line 8, a counting trigger 9, an element IS-10.11 - D-flip-flop 12, control block 13, key 14, formation channels 15, consisting of trigger 16 and two drivers 17, each of which contains an adder 18, random access memory (RAM) 19, counters 20, 21 pulses, D triggers 22-27, elements OR NOT 28-31, registers 32.33, multiplexer 34, controlled line 35 delays the data bus 36, address bus 37, output bus 38 timing output buses 39, 40, 41. Tires initial installation are not shown in the drawing. The value of the period Td of the generator 1 is selected in accordance with the weighting factor of the youngest of the bits of the codes received from RAM 5, 19 to the counters 20, 21 and block 13. The delay values of the links of controlled lines. 8.36 delays are selected in accordance with the weight coefficients of code bits coming from the lower bits of RAM 5 and 19 to adders 4 and 18. At the initial moment of time, the counter has 3 pulses, registers 6.7, counting trigger 9, D-flip-flops 22 -27, the trigger 16 is brought to the zero state, the D-flip-flop 12, the pulse counters 20 and 21 are set to one. In RAM 5 and 19, the codes of the required parameters of the pulse sequences are entered. In RAM 5, the codes of the values of the pulse following period on the synchronization bus 38 and on the buses 40 channels 15 are entered, in the RAM 19, in each of the channels 15, the codes of the values of the delayed position of the signal edge on the bus 40 of this channel signals, on the buses 40 other channels 15 , in RAM 19 of driver 17 in each of channels 15, codes of values of the delayed position of the cutoff signal on the bus 41 of this channel with respect to the other channels 15 are entered. When the device functions, change the control action on the address bus 36 with RAM. 5 and 19, codes are read that determine the values of the parameters of the pulse sequences on the buses 41 of the device channels 15. In this case, a real-time control mode is possible, when the values of the parameters of the delay, duration and period of the signal follow-up on buses 40, 41, channels 15 are determined in each successive follow-up period of the signals by setting the appropriate address control over the B bus in the next follow-up period. The device works as follows. When a command is sent over the data bus 37, the key 14 permits the passage of the reference frequency signals from the output of the oscillator 1 of the reference quartz frequency to the input of the programmable divider 2 frequencies. From the output of which, the signals without division or divided in a certain ratio (depending on control over data bus 37) are received in continuous sequence at the synchronization inputs of the counter 3 pulses, D-trigger 12 and the synchronization inputs of the counter 20 pulses, counter 21 pulses, D-triggers 23,24,26,27 each of the drivers 17, each of the channels 15. The signal level, logic O, coming from the direct output of the D-flip-flop to the control input of the 3-pulse counter, allows the information to be entered into this counter, and the unit level l allows the account mode to subtract. The entry of information into the counter 3 and the counters 20 and 21 is the signal received at the synchronization input of these counters, if there is a logic level at their control input. With the arrival of the first signal from the output of divider 2 frequency to the synchronization input of D-trigger 12, it is transferred from the initial state of the logical

1 at the direct exit to the state of lo-55 following them. Block 13 depending

O since, at this moment of control, it realizes two functions:

time to its D-input goes uro-if there is an input level of logical O from the count of logical 1 (if there is 3 pulses in the input. With the arrival of the second output from the adder 4), the reference frequency signal is entered into the counter arriving from the output of block 13. In this case, D-flip-flop 12 goes to the state of logical 1 at the direct output. Thus, a negative polarity signal is generated at the forward output of D-flip-flop 12. and at the inverse output is a positive polarity signal with the duration of TC, which enters the input of registering 6 and enters the code in this register, to the packpoint from the output of adder 4 (for the first period of signals on the device synchronization bus 38, this will be the code received from the lower bits of RAM 5, since the second inputs of the adder 4 receives the zero code from the output of register 6 brought into this state at the initial moment of time) and also goes to the input of the controlled delay line 8, at the inputs of which it is The zero code corresponds to the initial state of register 7. Therefore, with a delay corresponding to the zero control code (intrinsic delay), the signal from the input of the controlled delay line 8 arrives at the device synchronization bus 38 and enters the register 7 the transition of the signal from 1 to O code coming from the output of the register 6. In addition, having entered the first inputs of the elements AND-NOT 10.11, the signal from the inverse output of the D-flip-flop 12 passes through the element IS-NOT 10 and a negative level comes from the output of this item to the control input of the counter 20 pulses, the input is enrolled. The scientific research institute of register 33 and the synchronization input 0–, trigger 22. By changing the signal from level 1 to level O at the synchronization input of counting trigger 9, it changes its state to the opposite. At the initial time, address address 36 sets the address corresponding to the codes in RAM 5 and RAM 19, which determine the value of the first following period, as well as the values of the delay and duration of the signals on bus 40 of channel 15 in the first period of function f (A-1 if there is a logical O level at the control input, a function is implemented, where A is the code at the input of block 13 For the initial moment of time there is no transfer at the output of adder 4, since the second inputs are supplied with code 0000 from the output of register 6. Therefore, block 13 implements fun f 2. Starting from the third signal of the reference frequency at the synchronization input, the counter 3 pulses starts counting on the subtraction, continuing until the counter 3 clears, while the output of the counter 3 establishes the logic level O through the frequency reference clock is set at the output of the D-flip-flop 12. At this point in time, the outputs of the RAM 5 and the RAM 19 are installed by controlling over the address bus 36 codes that determine the parameter values of the pulse signals of the pulse sequence on the buses 39, 40, 41 channels 15 of the device torus period of the journey. If there is a level O at the control input of the counter 3 pulses, it is loaded with a code from the output of block 13. D-flip-flop 12 in the same clock cycle goes to logic level 1 at the direct output, and the signal from its inverse output enters No first control delay line and lingering on time S-6, where S. is the discreteness of setting the period of synchronization pulses, the code coming from the outputs of register 7 to the control inputs of the controlled delay line goes to bus 38. The same signal from the inverse the output of D-flip-flop 12 brings from the outputs of the adder to register 6, and also, having arrived at the first input of the element AND-NOT 11, the second input of which receives the logic level 1 from the direct output of the counting trigger 9, arrives at the logical input from the output of the element AND-NOT 11 to the control input pulse counter 21, to the input of registering the register 33 and the synchronization input of the D-flip-flop 25 of each channel 15. The signal from the device bus 38 also writes the code to the register 7. This ends the cycle of forming the first pulse period on the device bus 38. From the moment code is loaded into the counter of 3 pulses, the cycle of formation of the second pulse-following period begins. The formation of the position of the front and cut of the pulses at the output of the channels 15 is carried out in the following way. As indicated, the control inputs of the counters 20, 21 of the pulses are fed from the outputs of the elements AND-NOT 10 and 11. The logic level O at the control inputs of these counters allows the code to be entered into the counter with 1 high-order bits of the second RAM 19. After entering the codes into counters 20.21 allow counting mode to subtract; at the output of counters 20.21, the signal is released when they reach the zero state. Depending on whether there is a transfer at the transfer output of the adder 18, the D-flip-flops 22.25 are transferred to the synchronization input signal either to the logical 1 state if there is a transfer or to the logical O state when there is no transfer. Depending on this, the signal from the output of the counter 20 pulses is supplied through the OR-NOT element to the input of the D-flip-flop 26 without delay, or through the OR-NOT element with a one-cycle delay performed on the D-flip-flop 23. The signal from the D-input D-flip-flop 26 with a delay per cycle is fed to the input of a controlled delay line 36, which is delayed by a time proportional to the code entered in register 33. In registers 32.33 of the code is entered from the output of adder 18, to the first inputs of which code is supplied from the output of register 7, and to the second inputs - from the outputs of the low-order bits of the OZ 19. The signal from the D-flip-flop output also goes to the selection input of multiplexer 36 and switches multiplexer 34 through a time of not less than the maximum delay of the signal on the controlled delay line 35 so that it switches the code from the outputs to the controlled delay control inputs. registers 33. In the second period of the signals on buses 39-41 channels 15, loading the code from the 1 most significant bits of RAM 19 is carried out into a pulse counter 21, and from the outputs of the adder 18 into a register 33, 34. Otherwise, the counter 21 pulses elements W-30 and 31 D-tr 26.24 g .gerov and 25 is similar to the pulse counter 20, NOR 28,29, D-flip-flops 22,23,26. The signal from the output of the D-flip-flop 27 is fed to the input of the controlled delay line 35. The signals from the output of the control line 35 of the driver are fed to the bus 39 of channel 15 and to R - the input of trigger 16, thereby determining the position of the signal edge on the bus 40 of channel 15. Due to the fact that the counters 20, 21 of the pulses are loaded once over two periods of signals on bus 38. device synchronization, it is possible to form a delay and pulse duration on buses 39, 40, 41 channels 15 within two periods of their following. The work of all formers 17 is similar. From the output of the controlled delay line 35 of the driver 17, the signals are fed to the bus 41 of channel 15 and S is the input of the trigger 16, determining the cutoff position of the signal on the bus 40 of channel 15. Thus, on buses 38,39,40, 41 devices, pulse sequences of signals are formed with software controlled values of pairs of Q-meters of signals. On the device synchronization bus 38, signals of positive polarity are output, the period of which is determined by the state of the outputs of RAM 5, which can vary from period to period of follow depending on external control via address bus 36. On bus 40 of channel 15 signals are issued following with the same period of following, as on the tire 38 of the device. Moreover, the mutual position of these signals in different channels 15 relative to each other within a given follow-up period, namely the position of the front and the cut-off of the signal, is determined by the state of the outputs of the RAM 19 of the driver 16, respectively. Since the address bus 36 is connected to all the RAM in parallel,

the period of the following, the position of the front and cut of the synchronization pulses on all buses of the channels 15

the reference frequency inhibit time required to select a new reference frequency phase at the beginning of each cycle. walks at the same time (when the address control changes). In the event that the address control remains unchanged, the device generates pulse sequences in the normal generating mode, without changing the parameters of the signals from the period to the next period. On the tires 39 of the channels 15, the signals are issued synchronously with the position of the front and the cutoff of the pulse, respectively, on the bus 40 of the channels 15. Operation of the device in case divider 2 frequencies produce a frequency divided by the programmed coefficient, a multiple of the reference frequency coming from the generator 1 reference quartz frequency , similar to that described. The difference is that in m the lower bits of RAM 5 and RAM 19, zero information is programmed. The discreteness of the software setting of the parameters of the signals in this case is equal to the period of the signals at the output of the divider 2 frequency. Thus, in this device in comparison with the known, the formation of time parameters of the signal outputs of channels 15 with the required programming resolution S, much shorter than the period TO of the reference frequency signals, with the possibility of real-time control, is performed when the pulse counters and triggers are clocked in a continuous sequence reference frequency signals. This eliminates the components of the error in the formation of time intervals due to the selective choice of the phase of the reference frequency at the beginning of each cycle of the formation of wartime intervals inherent in the prototype. Also due to the fact that the signals of the reference frequency clocks the pulse counters in a continuous sequence, these pulse counters can work with conversion factors limited only by the technical characteristics of amix counters and not limited

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Claims (2)

1. MULTI-CHANNEL DEVICE FOR FORMING PULSE SEQUENCES, comprising a reference quartz frequency generator, a programmable frequency divider, the output of which is connected to the first input of the pulse counter, the first input of the programmable frequency divider is connected to the first input of the random access memory, the first output of which is connected to the first input of the adder whose output through the first register is connected to its second input and to the first input of the second register, the output of which is connected to the first input a split delay line, the output of which is connected to the second input of the second register, the second input of the controlled delay line is connected directly to the first inputs of the first and second AND elements, and through a counting trigger with the second inputs of the first and second AND elements, as well as the formation channels, the first input of each of which is connected to the output of the first NAND element, the second input of each formation channel is connected to the first input of random access memory, the third input of each formation channel is connected to the second one of random access memory devices, characterized in that, in order to improve performance and improve the accuracy of the device, a key, a control unit and a D-trigger are introduced into it, and the output of the second NAND element is connected to the fourth input of each formation channel, the first input D -trigger is connected to the first input of the pulse counter and to the fifth input of each channel of formation, and the second input is connected to the output of the pulse counter, the first output of the D-trigger is connected to the second input of the first register and to the input of the counting three hera, the second output of the D-trigger is connected to the second input of the pulse counter, the third input of which is connected to the output of the control unit, the first input of which is connected to the second output of random access memory, the second input of the control unit is connected to the output of the adder, and the first input of the key is connected to the output of the reference quartz frequency generator, the key output is connected to the second input of the programmable frequency divider, the second input of which is connected to the second input of the key, and the output of the second register is connected to the sixth input m each channel formation. 2. Multichannel device for the formation of pulse sequences pop. 1, characterized in that each shaping channel consists of two pulse shapers, the outputs of which are connected to the inputs of the trigger, and each pulse shaper contains an adder whose output is keyed to the first inputs of the first and second D-triggers, the first output of random access memory is connected with the first input of the adder, the second output of random access memory is connected to the first inputs of the first and second pulse counters, the second inputs of which are combined, the outputs of the first and second impu counters Lls respectively: connected to the first inputs of the third and fourth D-flip-flops and the first and second elements OR NOT, the second inputs of the third and fourth D-flip-flops are combined and connected to the second inputs of the pulse counters and to the first inputs of the fifth and sixth D-flip-flops , the second inputs of which are respectively connected to the outputs of the first and third elements OR-NOT and the second and fourth elements OR-NOT, the second input of the first element OR-NOT connected to the first output of the first D-trigger, the second output of which is connected to the first input. the third OR-NOT element, the second input of which is connected to the output of the second .D-trigger, the output of the fourth D-trigger is connected to the first input of the fourth OR-NOT element, the second input of which is connected to the first output of the second D-trigger, the second output of which is connected to the second input of the second element OR NOT, with the second input of the first D-trigger connected to the third input of the first pulse counter, to the first input of the shaping channel and to the first input of the first register, the second input of which is connected to the second output of the adder and to the first input the second register house, the outputs of which are connected to the first inputs of the multiplexer, the second inputs of which are connected to the outputs of the first register, the third input of the multiplexer is connected to the outputs of the fifth and sixth D-flip-flops and the first input of the controlled delay line, the second input of which is connected to the output of the multiplexer, the output is controlled the delay line is the output of this driver, pulses, the second input of the second register is connected to the second input of the second D-trigger, to the third input of the second pulse counter and to the fourth input near the formation channel, the first input of random access memory is the second input of the formation channel, the second input is the third input of the formation channel, the second input of the adder is the sixth input of the formation channel, and the second inputs of the pulse counters are the fifth input of the formation channel.