SU949821A1 - Rate scaler with variable countdown ratio - Google Patents

Description

(54) THE DIVIDER OF THE FREQUENCY RATING OF PULSES WITH A FRACTIVE VARIABLE DIVISION COEFFICIENT

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The invention relates to a pulse technique and can be used in automation and computing.

A known pulse frequency divider contains a pulse shaper, AND elements, a fill detector, 5 pulse counter, an integer setting block, a driver unit, a shift trigger, and an AND-OR element 1.

A disadvantage of the known device is low speed., Q

The closest to the present invention is a pulse frequency divider with a software task of a fractional division factor, containing a pulse generator, a programming unit, the first output of which is connected to the input of the decoder 15 of the fractional coefficient, and the remaining outputs to one of the digital comparator inputs, the other inputs of which are connected with the outputs of the integer coefficient counter, and the output with the first input of the switch, 2o phase shifting element, OR element, fractional coefficient counter, frequency decoder and valves, The first inputs of which are connected to the output of the pulse generator through the phase shifter, the second inputs to the outputs of the frequency decoder, and the outputs to the outputs of the OR element, the output of which is connected to the counting input of the integer coefficient counter and the second input of the switch, the output of which is connected to the zeroing input of the integer counter coefficient and with one of the inputs of the counter fractional factor 2.

The disadvantages of the known device are the low speed and the limited value of the integer part of the division factor.

The purpose of the invention is to increase the speed while simultaneously expanding the range of variation of the division factor by extending the range of control of the whole part of the division ratio.

This goal is achieved in that a pulse frequency divider with a fractional variable division factor contains a pulse generator, the output of which is connected to the input of the phase-shifting element, the outputs of which are connected to the first inputs of the first matching unit, the outputs of which are connected to the inputs of the first OR element, switch and a pulse counter, a second matching block, a memory register, a shift register, a delay element, an inverter, triggers, and AND elements, the inputs of the first of which are connected to the outputs, are entered The pulse generator, and the output, to the first input of the first trigger, the second input of which is connected to the output of the second element I, the inverse output to the first input of the second trigger, and the direct output to the first input of the third element I, the second input of which is connected to the output of the second the OR element and the inverter input, and the output to the second input of the second trigger, to the control input of the pulse counter, the first inputs of the shift register and the memory register, and through the delay element to the first input of the fourth element I, the second input of which is connected to the first output the house of the shift register, and the output with the clock input of the switch, the inputs of which are connected to the corresponding outputs of the memory register, the installation inputs of which are connected to the installation buses of the fractional part of the division factor, and the outputs with the second inputs of the first coincidence unit and the first inputs of the second coincidence unit, the second inputs of which are connected to the outputs of the phase shift of the element, and the outputs - to the corresponding inputs of the second element OR, the first input of the second element AND is connected to the output of the second trigger, the second the input is with the inverter output, the third input is with the second output of the shift register and the first input of the fifth AND element, the second input of which is connected to the output of the first OR element, and the output is connected to the counting input of the pulse counter, the installation inputs of which are connected to the code buses, and the first and second inputs of the shift register are connected to the control buses. The drawing shows a block diagram of the device. The device contains a pulse generator 1, a phase-shifting element 2, blocks 3 and 4 coincidence, a switch 5 of the fractional part of the division factor, elements OR 6 and 7, elements AND 8-12, a shift register 13, a counter 14 pulses of the integer part of the division coefficient, triggers 15 and 16, memory register 17 of the fractional part of the division factor, delay element 18, inverter. 19, the installation buses 20 of the code for the integer part of the division factor, the busses 21 and 22 for controlling the operating modes, respectively, Fraction and Integer, the tires 23-25 for setting the fractional part of the division factor, respectively, 1/4, 2/4, and 3/4. The device works as follows. The divider can work in three modes: division by mixed, integer and fractional numbers. When divided by the mixed number, the pulses of the generator 1 arrive at the input of element 2, where they are converted into pulses with frequencies FJ, F, Fj, F equal to the frequency of generator 1, but shifted relative to each other by 1/4 of the period. These frequencies arrive at the corresponding inputs of blocks 3 and 4. Blocks 3 and 4 pass one of the frequencies to their outputs depending on the state of switch 5 defined by registers 17 and 13. The control of blocks 3 and 4 of coincidence is organized so that the output frequency of the block 3 always leads the output frequency of block 4 by 1/4 of the period. The fractional part of the division ratio can be 1/4, 2/4, and 3/4 of a period. The fractional part of the division factor is set by applying to levels 23-25 for the ratio 1/4 - to bus 23, 2/4 - to bus 24, 3/4 - to bus 25. This level must be maintained until the coefficient changes. The integer part of the coefficient can take values from 1 to (1), where n is the number of bits of the counter 14. The value of the integer part of the coefficient is given by the code supplied to the buses 20. For the bus group 20, the coefficient is specified by writing to the counter 14 of the number N () - К where K is a whole part of the coefficient. Register 13 is intended to organize the operation of counter 14 in modes where the division factor is a mixed, integer or fractional number. When recording the coefficient, which is a mixed number, levels 1 are applied to tires 21 and 22. By a signal from the output of element 10, the codes installed on buses 20-25 are recorded from into counter 14, register 13 and register 17, and register 13 with levels “1 opens elements 11, 12 and 9 from its outputs, and register 17 with level“ 1 from one of the outputs prepares the operation of the switch 5 to the desired fractional part. Switch 5 is a four-bit cyclic shift register with varying connections between the triggers. These connections are set by levels "1 from the outputs of register 17 so that when a factor of 1/4 arrives at its input, the triggers switch sequentially one after the other, when a factor of 2/4 arrives at its other input, the triggers switch through one, and when a factor of 3/4 arrives, after two, and when the factor is changed, a new switching cycle starts in a predetermined order of the trigger that was switched to one state at the moment of switching. The output signals are removed from the direct outputs of the flip-flops, therefore, at the outputs of the switch 5, the levels “1” occur cyclically in accordance with the switching of the flip-flops. At the output of block 4, frequency pulses appear, shifted with respect to the previous one by the necessary part of the division factor.

The pulses of the sequence of the selected frequency from the output of block 3 through the element OR 6 and the open element And 12 enter the counter 14 before it is filled. The signal from the output of the AND 8 element that identifies the filling of the counter 14 switches the trigger 16, which opens the AND 10 element with the level “1 from the direct output, thereby preparing the output signal from the output of block 4 through the OR 7 element and the AND 10 element to the output.

The output signal of the divider from the output of the And 10 element records the new (or previous) division factor and operating mode and through the delay time 18 and the open element And 11 switches the switch 5. At the same time, the output signal switches the trigger 16, which by level "1 from the direct output opens An AND 9 element previously prepared for opening at another input by the level "1 from the output of the register 13. By the falling edge of the signal from the output of the element OR 7, through the inverter 10 and the open element AND 9, the trigger 15 is set to the zero state. A trigger 15 with a signal from the direct output closes the element 10, preventing the output signal from passing, and with a signal from the inverse output sets the trigger 16 to zero. The divider is ready for a new division cycle.

When divided by an integer, the level "1" is established only on the bus 22 of register 13, and the code of the integer part of the coefficient is fed to the bus 20. On the tires 23-25, the levels "O" are applied.

The level "O on the first output of the register 13 closes the AI element, which prohibits the passage of the signal to the clock input of the switch 5, and the second output of the register 13 sets (maintains) the level" 1, the opening elements AND 12 and D and the outputs of the register 17 are set The "O" levels, i.e., the switch 5 remains in the state it was in until the moment of switching, therefore, the block matching elements remain open and a new code is written to the counter 14. Otherwise, the divider works in the same way as described above.on a mixed number.

When divided by a fractional number, the level "1 is fed to the bar 21 of the register 13 and to one of the lengths of 23-25, depending on the given fractional coefficient. Tires 20 are supplied with levels of "1 (the whole part of the coefficient is zero).

At one of the outputs of the register 17, a level "1" is set up, which prepares the switch 5 to switch the fractional part of the coefficient to divide by a given fractional part, and the first output of the register 13 sets the level "O, which takes the elements 12 and 9, turning off the counter 14 parts of the division factor from block 3, as well as resetting the trigger 15 to the zero state. The counter 14 of the integer part of the coefficient retains the saturation state for the entire period as long as the whole part of the division factor is missing. Element And 8, which identifies this state, switches the trigger 15, which opens element And 10, allowing the output divider to pass to the output.

Thus, when dividing by a fractional division factor, counter 14, triggers 15 and 16, and elements 12 and 9 do not work, and element 10 is open all the time. The output signal through the delay element 18 and the open element 11 switches the switch 5, which opens the corresponding coincidence element of the block 4, passing one of the frequencies to the output through the elements OR 7 and AND 10 to the output. The magnitude of the delay element 18 must be equal to the delay time of one trigger.

Increasing the speed of the divider is achieved by organization using block 3

preliminary (for 1/4 part, period) preparation of the output signal circuits. In addition, such conditions of work of the divisor determine the protection of the divider from failures when changing the fractional part of the division factor. The proposed divider with a fractional variable division factor has a much greater speed than the known one, as well as a greater range of regulation of the whole part of the division factor.

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Claims (2)

1. USSR Author's Certificate No. 453803, cl. H 03 K 23/00, 1973. 2. USSR author's certificate number 621102, cl. H 03 K 23/00, 1977.