SU495771A1 - Digital device frequency tuning controlled oscillators - Google Patents

Description

one

The invention relates to the field of radio engineering and can be used in frequency synthesizers, radio communication systems and instrumentation.

A digital device for tuning the frequency of controlled generators is known, comprising a reference generator, the output of which is connected via a valve to one of the inputs of a frequency divider, another input of which is connected to one of the trigger inputs, the first output of which is connected to the second input of a valve, and the second trigger input is connected through a frequency divider with a variable division factor and a tunable oscillator with an output of a digital-to-analog converter, whose sign input is connected to one of the outputs of a frequency divider, desh ifrator and anti-coincidence scheme.

The proposed device makes it possible to reduce the tuning time of the controlled oscillators. This is achieved by the addition of a valve, a counter, and two anti-coincidence schemes. The output of the reference generator is connected via an additional valve connected in series, an additional counter, and two additional anti-lock circuits to one of the inputs of the anti-coincidence circuit; the second output of the additional counter is connected to one of the trigger inputs, the second output of which is connected to

the second input of the additional valve, the second outputs of the frequency divider are connected to the inputs of the decoder, and each output of the decoder is connected via an anti-clock circuit to the inputs of the digital-analog converter.

The drawing is a block diagram of the described device.

The device contains a divider 1 with a variable division factor, trigger 2, additional counter 3, divider 4 frequencies, additional 5 and 6 and main 7 anti-coincidence schemes, reference 8 and tunable P generators, gate 10, additional gate I, decoder 12 and digital-analog converter 13.

/ e - the reference frequency at the output of the reference generator 8;

fr is the output frequency of the tunable generator 9;

f „- - -fr is the frequency of the pulses at the output of t

divider 1; m is the division factor.

The device works on the principle of comparing1

No periods of TP and Go, where the Gd is the period

fn

pulse sequence at the divider output; UO - sequence period

/ e

pulses at one of the outputs of the divider 4

frequency, connected to the input of the digital-to-analog converter 13; n is the constant division factor of the frequency divider. The difference informationA To - T Т is weighted using the circuits 5-7 of anti-sow-5 drops and the digital-analog converter 13 and is fed to a tunable generator 9.

The frequency tuning fr begins with a change in the value of the division factor t. In this case, the next pulse from the output of the divider 1 is fed to the setup input of the trigger 2, tilting the latter to the state "1. As a result of the flip-flop of trigger 2, valve 15 10 is closed, fixing the state of the 4 frequency divider, and an additional valve 11 is opened, through which the additional (usually small-sized) counter 3 is filled with pulses from the reference generator 8. 20

Additional counter 3 has two outputs - forward and late. The impulse from the advanced output, depending on the state of the divider 4 frequency, fixed by the moment of arrival of the pulse from the output of divider 1 and decrypted by the decoder 12, passes through anti-coincidence circuits 5-7 to the corresponding bits of the digital-to-analog converter 13. Pulse from the delayed output of the counter 3 appears 30 seconds when the latter overflows and is fed to the installation inputs of the 4 frequency divider and flip-flop 2. As a result of this setting, a code is entered into the frequency divider corresponding to the capacity of the additional counter. ka 3 and trigger 35 in the tipped 2 state "O.

After the flip-flop 2 is tilted, an additional valve 11 is closed and the valve 10 is opened, through which the pre-installed frequency divider 4 begins to fill. With the arrival of the next pulse from the output of divider 1, the restructuring process is repeated.

Weighing the pulse from the advanced output of the additional counter 3 using 45 circuits 5-7 anti-coincidence occurs as follows.

If the 4 frequency divider operated in the free unsynchronized mode, then a sequence of pulses with the TO repetition period would occur at the input of the D / A converter 13, and gates with widths of 5-7 would be removed from the outputs of the decoder 12 to the anti-coincidence circuit 5-7 TZ and Гз (and, 55 are located symmetrically with respect to the pulses at the sign input of the digital-to-analog converter 13.

In the proposed device, the next pulse from the output of the divider 1 captures one of the 60

The four possible states of the 4 frequency divider.

In the first case, when the period difference (Dt) is 0.5 TI, the pulse from the advanced output of the additional counter 3 passes through the additional circuit 5 anti-coincidences to the higher bits of the D / A converter 13.

In the second case, 0.5 G2 (Dt) 0.5 TI and the specified pulse passes through additional circuits 5 and 6 of anti-coincidence on average bits of the converter 13.

The third case corresponds to the inequality of 0.5 Gz (Dt); 0.5 TZ, i.e., the indicated pulse passes through all the 5-7 anti-coincidence schemes for the younger bits of the converter 13.

In the latter case (Am), 5 Ha, i.e., another impulse from the output of divider 1 enters the Gz gate. In this case, the impulse from the leading output of the additional counter 3 is not supplied to the digital-apalalog converter 13, as a result of which the tunable generator 9 is in the free mode.

Thus, the proposed device provides a weighted control signal to the tunable generator 9 at a speed equal to the frequency of the pulses at the output of the divider 1.

Claims (1)

Invention Formula A digital device for tuning the frequency of controlled generators, containing a reference generator, the output of which is connected via a valve to one of the inputs of a frequency divider, the other input of which is connected to one of the trigger inputs, the first output of which is connected to the second input of a valve, and the second trigger input is connected through a variable division frequency divider and a tunable generator with a digital-to-analog converter output, the sign input of which is connected to one of the outputs of a frequency divider, a decoder, and An anti-coincidence circuit, characterized in that, in order to reduce the frequency tuning time, a valve, a counter and two anti-coincidence circuits are added to it, with the output of the main generator connected through an additional gate, an additional counter and two additional aptico-drops to one of the circuit inputs anti-coincidence, the second output of the additional counter is connected to one of the trigger inputs, the second output of which is connected to the second input of the additional valve, the second out The frequency divider is connected to the inputs of the decoder, and each output of the decoder is connected via an anti-coincidence circuit to the inputs of the digital-to-analog converter.