SU1622928A1 - Variable pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in frequency synthesizers, in automation devices where time interval control is required. The purpose of the invention is to increase the reliability of operation by providing a stable change in the pulse following period in a wide range, achieved by presetting the splitter 2 frequency pulses from the output of the reference frequency generator 1 and switching trigger 3 on the clock input from the output pulse of the overflow splitter 2 frequency. The device also contains a reversible counter 4, the generator 5 pulses. 4 il.

Description

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The invention relates to a pulse technique and can be used in frequency synthesizers, in automation devices where time interval control is required.

The aim of the invention is to increase the reliability of operation by providing a stable change in the pulse follow-up period in a wide range,

FIG. 1 shows a functional diagram of a controlled pulse generator; FIG. 2 is a diagram of a reference frequency generator; in fig. 3 is a diagram of the generator – torus pulses; in fig. 4 shows timing diagrams for the operation of the device.

The controlled pulse shaper contains a frequency generator 1, a divider 2 often. ,, trigger 3, reversible counter 4, generator 5 pulses.

The control inputs of the generator 1 are the control inputs of the device. The output of generator 1 is connected to the preset inputs of splitter 2 of trigger 3 and the counting input of the reversible counter 4, the outputs of which are connected to the control inputs of the generator 5, the output of which is connected to the counting input of splitter 2, the output of which is connected to the synchronization input of trigger 3, the information input of which is connected to potential logical units. The output of the trigger 3 is connected to the control input of the reversible counter 4.

The reference frequency generator 1 (Fig. 2) contains a rep /: tr b, counter 7, trigger 8, resistor 9, elements NOT 10 - 12, quartz resonator 13.

The inputs of the register b are the control inputs of the generator 1. The outputs of the register 6 are connected to the information inputs of the counter 7, the overflow output of which is connected to the information input of the trigger 8, the output of which is connected to the control input of the counter 7 and the output of the generator 1. Elements NOT 10 - 12 are connected in series. The output of the element 12 is connected to the counting inputs of the counter 7, the trigger 8 and through a resistor 9 to the input of the element 10 and the first output of the quartz resonator 13, the second terminal of which is connected to the output of the element 11.

The pulse generator 5 (FIG. 3) contains a register 14, a multiplexer 15, an AND 16 element, a multiplexer 17, blocks of the HE elements 18 and 19, a trigger 20, the HE element 21.

The inputs of register 14 are the control inputs of generator 5. The first output of register 14 is connected to the first input of element And 16. The second group of outputs of register & connected to the appropriate1

the control inputs of the multiplexer 17; the third output of the register 14 is connected to the control input of the multiplexer 15. The output of the multiplexer 17 is connected to the second input of the AND 16 element, the output of which is connected to the control input of the register 14 and the go of the block of HE elements 18, the output of which is connected to the inputs of the block of HE elements 19 and the element is NOT 21, the output of which

0 is connected to the clock input of the trigger 20 and the first input of the multiplexer 15, the second input of which is connected to the output of the trigger 20. The outputs of the block of elements HE 19 are connected to the corresponding inputs of the multi-plexer 17. The output of the multiplexer 15 is the output of the generator 5.

The device works as follows.

In the register 6, from the control input of the generator of the reference frequency 1, a code is entered that causes the initial state of the counter 7 (Fig. 2). The generator 1, which includes the elements NOT 10-12, forms a sequence of high frequency pulses

5 (FIG. 4e), which enters the counting inputs of counter 7 and t digger 8. Counter 7 counts the pulses arriving at its counting input, with i the initial state of counter 7 being caused by a code arriving at

0, its initial setup input is from register 6. At the moment of overflow of counter 7, a transfer signal is generated at its output (Fig. 46), which is fed to the information input of trigger 8. According to the synchronization pulse, trigger 8 is set to one state (Fig. 4c ).

The output signal of the trigger 8, the counter 7 is set to the initial state, corresponding to the control code on the input.

0 On the next high frequency pulse, trigger 8 is reset to its initial state and a pulse is formed at its output, then the cycle repeats.

As a result, a pulse sequence is formed at the output of the trigger 8, the follow-up period of which is determined by the code entered in register 6. The follow-up period of the generated pulse train is used as a reference time interval.

At the initial time, the frequency of the pulses of the generator 5 may be any of the range of possible values.

Divider 2 has a fixed conversion factor, according to which it generates an output sequence of pulses.

The counting input of the reversible counter 4 and the input of the installation in O splitter 2 and trigger 3 receive pulses from the generator 1,

defining the reference time interval. Assume that 64 output pulses of the device, i.e. the division factor of divider 2 is 64. Divider 2 reads pulses arriving at its input. If the overflow counting signal appears at its output before the zeroing of the divider 2 pulse from the generator 1 arrives at the input, i.e. before the end of the reference interval time | FIG. 4d) - trigger 3 in g is filled with one state (FIG. 4e)

The signal of the unit level from the output of the trigger 3 is fed to the control input of the reversible counter 4 and provides three E5LLS from the generator 1 pulse adding 4 units to the content of the reversing counter. At the same time, the control code at the exit of the cost estimator 4 and therefore, to the input Generator 5 is changed in the direction of decreasing the frequency of this generator (Fig. 4e, moments nt and h)

The same impulse from generator 1 sets divide 2 and trigger 3 to the initial state. Divide 2 starts the next counting cycle.

B if m an impulse from generator 1 goes to the reset of divider 2 before the end of the bill, i.e. Quantity: String of pulses deposited in the reference time interval is less than 64, the trigger state does not change and a zero level signal is output from its output. In this case, the unit subtracts the contents of the reversing counter 4. The code at the output of the reversing counter 4 changes in the direction of increasing the frequency of the generator 5 (Fig. 4e, time ta).

The pulse generator works as follows.

Once during the period of the generator 5 output signal, a pulse from the output of multiplexer 17 is connected to register 14 from the controlling generator 5 input, and the code determined by the state of the reversing counter 4 and controlling the connection of the m / lmplexg 17 inputs is recorded.

Assume that, when included in register 14, a code was recorded that connected the output of multiplexer 17 to the input connected to the output of the last NOT to the HE elements 19. From the output of the HE element 21, a sequence of pulses goes to the first information input of the multiplexer 15 and TRIG Trigger 0.

At zero under the control input of the multiplexer 15, the generated pulse sequence is fed through its first information input to the output of the generator 5 From the output of the generator 5

the formed pulse sequence is fed to the input of divider 2, where it is compared with a reference warrant interval. If the required frequency, determined by the reference time interval, is greater than the frequency of the generated pulse train, the code at the output of the reversible counter 4 is changed, and therefore, the control code is changed at generator 5 output. Each time, the code at the output of the reversible counter 4 is changed by one, and in the generator 5 the switching is carried out to the adjacent information input of the multiplexer 17. The discrete variation of the follow-up period of the output pulse-generator 5 in this case will be equal to 4 - Г - wherein (y- delay time of the signal during the passage of one element cheoez NOT HF 19 block elements.

With large periods of clock pulses from the output of generator 1, and therefore, with the large required periods of follow-up of the pulse pulses of generator 5, a situation may arise in which the adjustment of the frequency of the output pulses does not provide an increase in the number of connected elements NOT

In this beam, a code is set at the information input of the register 14, at which a third signal is set at the third output of the register 14, which connects the second information output to the output of the multiplexer 15. The pulses from the output of the element HE pass 21 through the trigger 20 and through the information input of the multiplexer 15 to the output of the generator 5. At the same time, due to the fact that the trigger 20 works as a divisor by two, the period of the output pulses is doubled (Fig. 4i). Further, the tracking of the period of the output pulses of the generator 5 is carried out in the same way as described. The initial installation of the ring oscillator is provided by writing to the register 14 a code prohibiting the passage of a signal through the element 16.

Claims (1)

Formula of inventions A controlled pulse shaper containing a frequency generator 1 whose output is connected to a preset three input, a ger, a reversible counter, a pulse generator whose output is connected to a counting input of a frequency divider, characterized in that, to increase reliability, the output of the reference frequency generator is connected to preset delle frequency gel input and counting input of a reversible counter outputs which is connected to the control inputs of the pulse generator, the overflow output of the frequency divider is connected to the clock input of the trigger, whose information input is connected to the potential of the logical unit, the output of the trigger is connected to the control input of the reversible counter. Fig.Z Phie. 2 w; PLLLDLL-GG, vrujjin, it-gi1p Hz -CN-Mon