SU1167708A1 - Device for generating pulses - Google Patents

Description

About 00

The invention relates to a pulse technique and can be used in the design of digital devices with variable temporal characteristics.

A device for generating sync pulses is known, which makes it possible to tune the parameters of all pulses simultaneously and independently of each other. For this, there is a formation unit, a shift register, a master oscillator, a switch unit, a control register 1.

The drawback of the device is the large control word width, which leads to an increase in the equipment of both the pulse shaper itself and the device controlling its operation.

The closest to the technical essence of the invention is a device for generating pulses, comprising a master oscillator, the output of which is connected to the counting input of a pulse counter, the first group of outputs of which is connected to the address inputs of the memory block, the buffer register, the OR element, output triggers. 12.

This device allows you to adjust the parameters of all clock pulses simultaneously and independently of each other and to quickly switch from one series of pulses to another by setting the transition address buffer register.

The drawback of the device is that the range of adjusting the duration of the pulses is limited by the storage capacity of the device and the expansion of the storage capacity is required for its expansion, which leads to an increase in equipment.

The purpose of the invention is to expand the range of adjustment of the pulse duration and increase reliability.

The target is achieved by the fact that a pulse generator device containing a master oscillator, the output of which is connected to the counting input of a pulse counter, the first group of outputs of which is connected to the address inputs of the main memory block, the buffer register, the OR element, the first input of which is connected to the control input of the device, output triggers, additionally entered a memory block and a block of elements AND, the outputs of the buffer register are connected to the installation inputs of the counter and pulses, the control input of which is connected via the OR element to the output of one of the output triggers, the synchronization inputs of the output triggers are connected to the output of the master oscillator, the first and second inputs of each of the output triggers are connected to the corresponding outputs of the block of elements AND, the first and second groups of inputs are connected respectively to the information outputs of the main and an additional memory block, the address inputs of an additional memory block are connected to the second group of pulse counter outputs.

The drawing shows a block diagram of a device for generating pulses. The device for forming pulses consists of master oscillator 1, buffer register 2, pulse counter 3, element OR 4, first (main) and second (additional) memory blocks 5 and 6, block 7 of AND elements and output flip-flops 8,

0 for example LC-triggers. The first input of the OR 4 element is the control input of the device. The address input of the device is the input of the buffer register 2, the output of which is connected to the installation input of the counter 3, the counting input of which is connected

5 with the output of the master oscillator 1, and the control input is connected to the output of the element OR 4. The outputs of the lower and upper bits of the counter 3 are connected, respectively, to the address inputs of the first and second

Q blocks 5 and 6 of memory, whose information outputs are connected, respectively, with the first and second inputs of the corresponding elements And block 7, whose outputs are connected to 3; and To the inputs of the output trigger 8, the synchronization inputs of which

5 is connected to the output of the master oscillator 1, the output of one of the triggers 8 is connected to the second input of the element OR 4, and the outputs of the other triggers 8 are the outputs of the device.

0 The device operates as follows. Before starting work, the device is pre-configured: when using a random access memory as blocks 5 and 6 of memory, information about the parameters of all pulse series is loaded; when using a permanent storage device as blocks 5 and 6, the address of the initial cell of the array containing information about the selected pulse grid is specified.

For this, the signal at the control input of the device, the counter 3 is switched to the installation mode, thereby prohibiting the counting of the pulses of the master oscillator 1 and the address from the address input of the device is entered into the buffer register 2 and the counter 3. The lower part of the address goes to the address input of the main memory block 5 , senior - to the address input of an additional block of 6 memory. Information from the initial cell through the block 7 elements And comes

0 to inputs i and K of the output triggers 8 and entered into them when the synchronization pulse arrives at their inputs from the output of the master oscillator 1. At the outputs of the triggers 8, the initial values and pulses of the pulses are set.

Rattor 1; from blocks 5 and 6 of memory with the frequency of changing the address coming from counter 3, the data is sampled and, in accordance with the data, the pulses are formed at the outputs of the output triggers 8. The pulse series is completed when the signal at the second input of the OR 4 element appears, coming from the output of one of the output triggers 8. This signal passes through the element OR 4, transfers the counter to the installation mode and rewrites the contents of the buffer register 2 into the counter 3.

If the starting address of the same series is stored in buffer register 2, the formation of the pulse sequence is repeated until the signal appears at the control input of the device causing it to stop.

If the address of the final cell of the selected series is set in buffer register 2, then the signal programmed in the final cell is not received at the second input of the OR 4 element; the device will stop.

If in the buffer.m register 2 the starting address of the new pulse series is set, the next cycle of pulse train formation will begin.

Expansion of the range of control of the pulse duration, both in the proposed technical solution and in the well-known

achieved by increasing the capacity of the memory blocks. But with the same ysvov x, the proposed technical solution allows to obtain a control range much wider. The introduction of the second block 6 5 of memory and the blocks of 7 elements And creates two scales for setting the time parameters of the pulses. The exact position of the pulses is given by the data in the first block of the 5th memory, the coarse position in the second block of the 6th memory. Price

Q of one division of the first scale At is equal to the coefficient of recalculation of the lower bits of counter 3. The price of one division of the second scale is determined by the frequency of changing information in the higher bits of counter 3. In this case, the range of variation of the duration of intervals of a series of pulses is determined by the formula At- (P | - pg), where P | - the capacity of the first memory block 5; pa - the capacity of the second memory block 6. The total capacity of the memory in the proposed technical solution, as follows from the formula, is equal to the product of the containers

0 first 5 and second 6 memory blocks. While in a known device, an increase in the capacity of the memory block is equivalent to the summation of the available one.

Thus, the present invention, in comparison with the known, allows varying the range of control over the duration of a series of pulses with increased reliability within wide limits.