SU1566335A1 - Digit generator of piece-linear functions - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-precision programmable low-frequency function generators, approximated by piecewise linear segments. The purpose of the invention is to provide the possibility of adjusting the amplitude of the output signal of the generator in digital form. The generator includes a driver 1 of address, a block of 2 memory, accumulating adder 3, a generator of 4 clock pulses and a controlled frequency divider 5. The task of adjusting the output signal of the generator by controlling the number of integration cycles of elementary increments of the amplitude of the segments is solved by introducing a controlled frequency divider 5. 1 il.

Description

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The invention relates to computing and can be used in the construction of high-precision programmable low-frequency function generators, approximated by linear segments.

The purpose of the invention is to provide the possibility of adjusting the amplitude of the output signal of the generator in digital form.

The drawing shows a functional diagram of a digital generator of piecewise linear functions.

The generator contains the address driver 1, memory block 2, accumulating adder 3, 4 clock pulse generator and controlled frequency divider 5, output 6, inputs 7 and 8.

Before the operation of the generator, information on the length parameters, the magnitudes of the elementary amplitude increments and the sign of the increments of the linear segments approximating the given function should be entered in the memory block 2. Information on the parameters of the last segment should contain a sign of the end of the function.

The accumulating adder 3 must be set to its initial state (the circuits for entering information into memory block 2 and setting the accumulating adder 3 to the initial state are not shown in the diagram).

 The generator works as follows.

The start signal at input 8 starts the generator 4 clock pulses. Address generator 1 generates the address of the parameters of the current segment, from which memory block 2 reads the segment length code, arriving at the control input of address shaper 1, amplitude increment code, amplitude increment sign and segment increment sign, arriving at the corresponding inputs of accumulator 3 .

The segment length code determines the number of clock pulses of the generator 4, which must arrive at the counting input of the driver 1 before the address of the next segment is formed at its output. This amount to them

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five

thirty

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lane summer 3 and determine the number of cycles of summation of the code of the elementary increment of the amplitude of the current segment. The summing sign is determined by the segment increment sign.

The change in the division factor of the frequency divider 5 carried out at input 7 allows the number of pulses coming from the counting input to the output of divider 5 to change and, thus, adjust the number of cycles of summation of the elementary increment code of the segment in the accumulating adder 3 and accordingly all subsequent segments, and, ultimately, the amplitude of the entire function.

After processing the parameters of the current segment, at the output of the imaging unit 1, the address of the parameters of the next segment appears, along which the parameters of the segment are read in the same way as described from memory block 2, and so on, until the parameters of the last segment are processed. Upon completion of testing the parameters of the last segment at the output of memory block 2, a sign of the end of the function is formed, which is fed to the input of the generator 4 clock pulses and stops it.

The formation of the function ends there.

Claims (1)

Invention Formula A digital piecewise linear function generator containing an address driver, a memory block accumulating an adder, a clock pulse generator, wherein the output of the address code of the segment of the address former is connected to the address input of the memory block, the output of the segment length code of which is connected to the control input of the address former, .the output codes of the elementary increment of the amplitude and the sign of the increment of the segment are connected to the information and control inputs of the accumulating adder, the output of which is connected to the output of the generator, d terminator function block memory connected to the input shutdown n pulses enters the process of forming a clock pulse generator, the output of which is connected to the counting input neither the current segment from generator 4 to the counting input of the splitter 5 frequency. Pulses from the output of the frequency divider 5 are fed to the clock input on the address address accumulator, the input, the start of the clock pulse generator is connected to the generator start input, about driver address, input, start the generator of clock pulses connected to the start input of the generator, tl i515663356 due to the fact that, for the purpose of the frequency divider, the output of the amplitude of the output cog-th is connected to the clock input of the makapnal of the generator, the control adder is inserted into it A lyable frequency divider, with the controlled frequency depntl pop-up of the clock pulse generator to the input, the amplitude reference is sub-connected to the counting input of the control signal of the generator.