SU655074A1 - Variable division factor frequency divider - Google Patents

Description

The invention relates to radio metering and computing, in particular, to the conversion of information in frequency form.

Known frequency dividers with a variable division factor of 1, 2.

The known device 1 contains two identical divisions of the periods of the pulse signals.

For automatic division by any integer number of time intervals, each of the division channels contains a controllable divider by a given division factor, a counter for the number of scale units of the reference generator in the strobe of the dividend period, an ohmic decoder for the unit count results and a tracking divider with an automatically set division factor.

However, this device does not allow one to divide time intervals into fractional numbers, which does not allow one to obtain a linear law of variation of the pulse frequency at the output of the device.

The closest technical solution to the invention is a frequency divider with a variable division factor, containing frequency dividers, a census device, a divider setting unit, a trigger and AND elements, the first input of the first of which is connected to the input source, and the output to the first input of the first frequency divider, the bit inputs connected to the bit outputs of the unit for setting the division factor, the first output of which is connected to the first inputs of the first trigger, and the bit inputs of the second divider connected to the discharge frequency dnymi outputs census device.

The disadvantage of this device is the non-linear law of variation of the output frequency as a function of time.

The purpose of the invention is to provide a linear law of frequency variation as a function of time.

The goal is achieved by the fact that the frequency divider with a variable division factor, containing frequency dividers, a census device, a division factor setting unit, triggers and elements AND, the first input of the first of which is connected to the input source, and the output to the first input of the first divider frequencies, bit inputs connected to the bit outputs of the dividing rate setting unit, the first output of which is connected to the first inputs of the first trigger, and the bit inputs of the second trigger. the frequencies are connected to the bit outputs of the census device, a counter and additional elements I are entered. The input of the second frequency divider is connected to the output of the first element I, and the output to the first inputs of the second and additional elements I. The outputs of additional elements I are connected to the inputs of the installation unit the delpi coefficient, the second output of which is connected to the second input of the first element I, and the output of the second element I - with the input of the counter, the output of which is connected to the second input of the first trigger and to the installation input v trigger, whose direct output is connected to the first input of the census device and to the second input of the first additional element I, the inverse output to the second input of the census device and to the second input of the second additional element I. The direct output of the first trigger is connected to the second input of the second element P, and inverse - to the third input of the second additional element I.

The drawing shows a structural electrical frequency divider circuit with a variable division factor.

The variable divider frequency divider contains a frequency divider 1 with a fractional variable division factor, a variable frequency divider 2 with a variable division factor, a census device 3, unit 4 for setting the division factor, triggers 5, 6, And 7-10 elements, input source 11, counter 12.

Device 3 of the census has two microcircuits, four elements each in each. The first inputs of the elements And connected to the device dialing codes. The direct output of the second trigger 6 is connected to the second inputs of the first microcircuit, and its inverse output is connected to the second inputs of the second microcircuit.

The unit 4 for setting the division factor is made, in particular, on the basis of a reversible counter with t bits. The output of the first additional element And 9 is connected to the summing input of the reversible counter, and the output of the second additional element And 10 - with the subtractive input of the reversible counter.

The initial division factor of the frequency divider 1 is set by setting the initial state of the reversible counter triggers with a code set device. For fixing the maximum frequency dependence (0 and the signal of the end of the formation cycle, 2 tons of elements were entered into the dividing ratio setting block, the first inputs of which are connected to the device paborki codes, and the second - with the corresponding outputs of the bits of the reversible counter. One group of m elements And through the element OR beeps.

corresponding to the maximum frequency dependence (t), which is then sent to the first input of the first flip-flop 5. The second group of AND, OR elements also allocates the signal of the end of the formation cycle, which is then sent to the second input of the first And 7 element. The device follows in a way.

At the initial moment, the census unit 3 (female 13) is recorded with a code of two dividers - L and La, which correspond to the angles of the rising and falling sections of the frequency dependence (t}.

In block 4, the external control signals (female 14) set the initial Ls and the final Nn division factors

0 divider 1 frequency corresponding to the minimum and maximum frequency dependence (t}, and in the counter 12 external control signals (female 15) - conversion factor corresponding to the length of the horizontal section of the frequency dependence (/).

By the command “Start (bus 16) the frequency of the source AND input signal (/ o) is fed to the inputs of dividers 1 and 2 frequencies. From the output of the divider 1 frequency for

N,

/about

In modern time

frequency removed

/ 0 N,

The pulse occurrence at the output of the splitter 2 frequency through the ele, Mept I 10 increases the content of the code in block 4 of the setting of the division factor, the division ratio of the frequency divider 1 changes during the next interval

time -7 from the output of the divider 1 frequency

/ (

frequency removed. Magnification process

four

the frequency continues until the division factor 1 of the frequency-Lp is established. At this moment, in block 4 of setting the division factor, a pulse is formed, which, arriving at the input of trigger 5, transfers it from a bullet state to a single state. The inverse output of the trigger 5, acting on the first input of the second additional element And 10, locks it. In this case, the priming code in the block for setting the division factor is stopped, and the frequency divider 1 sets a constant division factor A, determining the beginning of the formation of the horizontal portion of the frequency dependence (i). At the same time, the direct output of trigger 5 acts on the second input of the second element I 8 and opens it. Impulses

frequency --G- through the first input element And 8