SU1354386A2 - Digital frequency multiplier with variable multiplication ratio - Google Patents

Abstract

This invention relates to radio engineering and improves the accuracy of frequency multiplication. The device contains quartz g Mr. 1, differential circuit 2, electr OR 3, controllable delay line 4, divider 5 frequencies with variable coefficient. dividing, ele- tine 6, shift register 7, memory register 8, decoder 9, driver 10 of control signals. Shapers 11 and 12 pulses, block 13 period comparison and integrating link 14. 1 Il. hch

Description

The invention relates to the field of radio engineering and communications, and can be used in devices for generating sync signals and is an improvement of the known digital multiplier with a variable multiplication factor according to auth.s. №67А190

The purpose of the invention is to increase the frequency multiplication accuracy.

The drawing shows a structural electrical circuit of a digital frequency multiplier with a variable multiplication factor.

The variable frequency multiplier with a variable multiplication factor contains a crystal oscillator 1, a differentiating circuit 2, an OR 3 element, a controllable delay line 4, a frequency divider 5 with a variable division factor, an AND 6 element, a shift register 7, a memory register 8 the decoder 9, the driver of the control signals 10, the first and second drivers of 11 and 12 pulses, the block 13 of the period comparison and the integrating link 14.

The digital multiplier works as follows.

The input pulses are fed to the input of the differentiating circuit 2, from the output of which the differentiated pulses through the element OR 3 arrive at the controlled delay line 4 and

to the control input of the deductor 5. The last one gives permission for the passage, the output of pulses from the output of the controlled line 4 delays to the counting input of the divider 5 and through the element AND 6 to the second input of the element OR 3. The operation cycle lasts until until divider 5 counts the number of pulses equal to its division factor, and then breaks the impulse feedback circuit, since its output has a logical zero level by which AND 6 closes. At the output of a digital multiplier with a variable multiplication factor impulses uniformly p placed in the period of the input signal. The value of the input frequency is determined by writing the number of pulses from the output of the crystal oscillator 1 to register 7 for the period of the input signal. The resulting binary code is rewritten at the next input pulse in register 8, where it is stored for the next period, the input frequency, and then

arrives at the decoder 9. In the decoder 9, the binary code of the register 8 and the division factor 5 determine the control signal by which the required delay time is set in the controllable delay line 4.

If the uniformity of the output pulse sequence corresponds to the required one, then the N-th pulse of the stack (where N is the division factor of divider 5) coming from the output of divider 5 through the second driver 12 to the second input of the comparison unit 13, the next input pulse coming from the output of the differentiating circuit 2 through the first driver 11 to the first input of the comparison unit 13, coincide, and at the output of the comparison unit 13 the error signal is zero. At the same time, the signal from the output of the integrator 14 at the input of the shaper 10 does not change, which means that the control signal at the shaper 10 output does not change and the crystal oscillator 1 operates at the same frequency.

When the output impedance sequence is violated, the pulses at the first and second inputs of comparison unit 13 do not coincide in time, and an error signal that is not equal to zero appears at the output of comparison unit 13. This error signal through the integrating link 14 is fed to the input of the generator 10. The latter, in turn, affects the frequency of the quartz oscillator 1 so as to eliminate the temporal mismatch of the pulses at the inputs of the comparison unit 13.

about

Formula of the invention Digital frequency multiplier with variable multiplication factor according to auth.St. No. 674190, characterized in that, in order to increase the frequency multiplication accuracy ,. Between the output of the differentiating circuit and the control input of the crystal oscillator, the first pulse generator, the period comparison unit, the integrating link and the control signal generator, and the second pulse generator, the input of which is connected to the divider output with a variable division factor, are entered, and the output of the second pulse driver is connected to the second input of the period comparison unit.

Claims (1)

Claim Digital frequency multiplier with variable coefficient of multiplication by auto No. 674190, characterized in that, in order to increase the accuracy of frequency multiplication, between the output of the differentiating circuit and the control input of the crystal oscillator are introduced serially connected first pulse shaper, a period comparison unit, an integrating link and a shaper of control signals, and a second pulse shaper is introduced , the input of which is connected to the output of the divider with a variable division coefficient, and the output of the second pulse shaper is connected to the second input of the period comparison unit.