SU1196940A1 - Simulator of radio signals - Google Patents

Abstract

RADIO SIMULATOR, containing a series-connected master oscillator, timing diagram generator, envelope signal generator, modulator, filter and interface block whose output is a simulator output, and a carrier frequency generator whose input is connected to the master oscillator output and the output is from the second input of the modulator, characterized in that, in order to improve the accuracy of the simulator, a sequential included descriptor, a register, a key block and an adder, the output of which is connected to the third in the modulator stroke, the decoder input is connected to the second output of the carrier frequency generator.

Description

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The invention relates to automation and computing, in particular, devices designed to train radio operators, including navigators, working with equipment that ensures safe driving of vehicles, allows you to determine the location from received radio signals, and also devices for reproducing in laboratory conditions, radio signals that may occur under actual conditions, and is used to test radio equipment.

The aim of the invention is to improve the accuracy of the simulator by increasing the stability of the parameters of the signals as the environmental conditions change.

FIG. G shows the functional scheme of the proposed device; in fig. 2 and 3 - time diagrams; in fig. .4 but - nodes and simulator blocks.

The device contains a master oscillator, a shaper of 2 time diagrams, a converter of 3 pulse waveforms, a filter 4, a conjugation unit 5, a carrier frequency generator 6, and the converter 3 consists of a shaper of an envelope signal and a modulator 8 connected in series. One of the inputs of the modulator 8 is connected to the input of the generator 6 directly, and the other input of the modulator 8 is connected to the generator 6 through a series-connected decoder 9, a register 10, a block 11 of keys and an adder 12.

The blocks 6-12 consist (of FIG. 5) of the flip-flops 13, the transistors 14 and 15, the resistors 16, the elements I 17 and the capacitors 18. the capacitors 18 ..

The simulator of radio signals works as follows.

The signal of the generator 1 is fed to the shaper 2, and, from the output of the latter, to the converter 3, pulses are fed, the order of which corresponds to the timing diagram, i.e. order of the pulses of the simulated signal.

When the next pulse arrives from the imaging unit 2 to the transducer 3, the latter begins to form the leading edge of the simulated radio pulse signal, the shape of the leading edge is determined by the imaging unit 7, and the carrier frequency is determined by the generator signal 6 supplied to the modulator 8. On the other. The second input of the modulator 8 additionally supplies a signal from the bits of the frequency divider of the generator 6 through the serially connected decoder 9, the register 10, the key block 11 and the adder 12. This chain of functional units ensures the formation of a periodic impulse / beat signal providing interpolation of the signal being formed inside each half cycle carrier signal

similar to that shown in FIG. 26, this signal differs from the signal of known devices (Fig. 2a) by a factor of 4-5 by a more favorable ratio of useful and side 5 components in the generated signal.

The pulse signal thus generated is output through block 5 and filter 4, filtering out the side high-frequency components.

Since the level of side components in the formed signal is several times lower than during half-period interpolation, in particular, the level of the nearest harmonic components decreases, for example, the third output signal when using a wideband filter is 4-5 times closer to ideal. Thus, it is possible to improve the quality of the simulated signal or use a simpler filter that contains fewer elements, is simpler to configure and more stable when environmental conditions change.

As the generator 1 can be used a generator stabilized by quartz, for example, a standard generator 5 of the type “Hyacinth.

The shaper 2, which determines the period of following the simulated signals, their number in the period and their mutual temporary position on the signal period, is realized as a splitter-counter and a decoder (not shown). At the same time, the divider determines the period of the generated signals, and the decoder connected to the divider bits determines the number of pulses in the period and their mutual temporary position.

The generator 6 is implemented in the form of a frequency divider of the signal of the generator 1, for example in the form of a binary counter (Fig. 4). The decoder 9, connected to the bits of the divider counter, can be implemented in the form of combinational logic elements And (Fig. 4).

The keys of the block 11 can be made differently, for example in the form of current switches, on transistors (Fig. 4). Keys of this type operate in an unsaturated mode and do not generate current pulses in the load with minimal delay and with little or no change in their attachment to the one given by the decoder signals 9.

The signals from the outputs of the key block 11 are fed to the adder 12, performed on resistors (Fig. 4), where they are summed, and then fed to the input of the modulator 8, at the input of which the signal is formed (Fig. 26) with step interpolation according to half period.

5 Shaper 7 is implemented as a transverse filter that forms an output pulse of a predetermined shape when an input pulse arrives (for example,

FIG. For, b). It can be implemented on the delay line, the shift register and the weight resistors connected to the taps of the delay line or the outputs of the shift register bits.

Pulse-type modulator 8 is performed on transistors, for example, according to the circuit shown in FIG. 5. The trigger 13 generates a symmetric pulse signal from a periodic pulse signal from the generator 6. From the trigger 13, the carrier signal is fed to the current switch on the transistors 14 connected via the emitter to the current-carrying transistor 15. The emitter current of the transistor 15 is set by a signal from the formate .L 7. The signals from the keys of the block 11 are fed through the adder 12 into the base circuit of transistor 15, the resistive divider in the base circuit sets the offset and acts as a signal adder - current adder: a step is formed on the base th interpolation signal (FIG. 26), so that the emitter current tranFig.

Sistor 15 varies in accordance with the shape of the interpolating signal at its base and in accordance with the change in the signal in the emitter circuit. The output pulse signal from the collector circuits of the transistors 14 is fed to a wideband bandpass filter 4, implemented, for example, on LC circuits (Fig. 5). From the output of filter 4, the signal goes to block 5, which is performed as a standard amplifier, signal attenuator, etc.

When using a wideband filter, the bandwidth of which is 3 times more than the signal spectrum policies, the uroen of side components in the output signal is reduced 4-5 times from 9-II to 2-3%.

Thus, the proposed device provides a more accurate signal imitation while increasing the stability of its parameters when the ambient temperature, humidity, etc. change. // g / ffjre block a 8

From the register formate / l 7 envelope

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Claims (1)

A RADIO SIGNAL SIMULATOR, comprising a serially connected master oscillator, a timing driver, an envelope signal generator, a modulator, a filter and an interface unit, the output of which is the simulator output, and a carrier frequency generator whose input is connected to the output of the master oscillator and the output to the second input modulator, characterized in that, in order to improve the accuracy of the simulator, sequentially connected decoder, register, key block and adder are introduced into it, the output of which is connected to the third input modulator, the decoder input is connected to the second output of the carrier frequency generator. SU., “1196940 FIG. 1