SU1385261A1 - Phase shifter - Google Patents

Abstract

The invention relates to radio engineering and can be used in instrumentation and frequency synthesizers. The purpose of the invention is to improve the accuracy of the formation of a phase shift. The phase shifter (PV) contains a phase control unit made in the form of a digital frequency synthesizer (CS), a band-pass filter 2, an adder 3 codes, a switch 4, a shift register 5, a gate shaper 6, and frequency dividers 7.8 with a variable coefficient. division. The frequency and phase of the output signal is determined by the code generated by the adder 3 as a result of the addition of the output frequency code and the change code of the output frequency. To change the output signal, the output frequency and time change frequency are adjusted. This is done by applying the output frequency change code through the shift register 5, switch 4 and adder 3 to the control input of the CS I for the time that the switch opens with 4 gates driver 6. Divider 7 determines the time during which the code of the output frequency is changed. Divider 8 determines the clock frequency with which the phase adjustment takes place. 2 ill. with € (L

Description

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The invention relates to radio engineering and can be used in instrumentation and frequency synthesizers.

The purpose of the invention is to improve the accuracy of the formation of the phase shift.

Fig. 1 shows a functional electrical circuit of a phase shifter; 2 is a functional electrical circuit of a digital frequency synthesizer.

The phase shifter contains a phase adjustment knob, made in the form of a digital frequency synthesizer 1, a band filter 2, a code adder 3, a switch 4, a shift register 5, a gate generator 6, a frequency divider 7 with a variable division factor, and an additional frequency divider 8 with a variable factor dividing, the digital frequency synthesizer 1 being implemented on a pulse shaper 9, a pulse elimination unit 10, a frequency divider II with variable division ratio, controlled delay line 12, trigger 13 and adder 14.

Phaser works as follows.

A digital frequency synthesizer 1 generates an output signal with a frequency and a phase defined by a code that comes from the outputs of the bits of the adder of 3 codes to the corresponding control bits of the digital synthesizer I frequencies and is formed by adding the change codes of the output frequency and output frequency , arriving respectively on the first and second inputs of the bits of the adder 3 codes.

The output phase of digital frequency synthesizer 1 is associated with frequency, frequency variation, and time

 fe. ,, j (wbb.) dt.

however, a change in phase due to a change in frequency over time & t is

50

L Cf JiO ut.

To change the phase of the output signal by the value of & cf in the phase shifter, adjustments are made to changes in the output frequency des and the time change in frequency & t.

Changing the output frequency by the value of d about and the time of changing the output

with

i o

15 20 25

0

h 0

j

0

g

Frequency & t is performed by applying a code for changing the output frequency through shift register 5, switch 4 and adder 3 codes to control inputs of digital frequency synthesizer 1 for time ut for switch 4, the opening time of switch 4 is determined by the duration of clock pulses arriving at the control input of the switch 4 from the output of the former 6 gates.

The duration and frequency of the clock pulses are determined by the signals of the pulse sequences with frequencies f, and the clock coming from the outputs of frequency divider 7 with variable division factor and additional frequency divider 8 with variable division factor forming the output signals from the pulse output signal of the digital frequency synthesizer 1, which through the band-pass filter 2 enters the output of the phase shifter. Divider 7 frequency with a variable division factor determines the time ut during which the output frequency code changes, and when changing the division factor of the divider 7 frequency with a variable division factor, the value of the generated phase shift Lif is changed during the clock period. frequency ftaKT which is determined by the division factor of an additional frequency divider 8 with a variable division factor, i.e. An additional frequency divider 8 with a variable division factor determines the clock frequency with which the phase adjustment is performed. By changing the division factor of the additional frequency divider 8 with a variable division factor, it is possible to carry out phase adjustment in a system with any inertia. At the same time, the accuracy of the phase shift being measured does not depend on the inertia of the device, i.e. from the passband of the band 2, and is determined by the stability of the input signal and the frequency grid of the digital synthesizer 1 frequency, since the magnitude of the frequency change is equal to or proportional to the frequency grid of the digital frequency synthesizer 1, and the closure time At is the time of the output frequency - formed from the output of digital frequency synthesizer 1 using a 7 4actoTbi divider with a variable division factor.

Digital frequency synthesizer 1 (FIG. 2) contains pulse generator 9 connected in series, block 10 excludes pulses, frequency divider 11 with a variable division factor, controllable delay line I2 and trigger 13, as well as adder 14, the first output of which is connected to the control Pulse exclusion unit 10 input, code output - outputs of the bits of the adder 14 - are connected to the control inputs of the bits of the controlled delay line 12, and the first input and inputs of the bits of the adder are connected respectively to the output of the controlled line 12 delays and to the outputs of the bits of the adder 3 codes that control the fractional part of the division factor of the frequency divider 11 with a variable division factor, and the control inputs of the bits that control the whole part of the division factor of the frequency divider 11 with a variable division factor, are connected to the corresponding outputs, . bits of the adder 3 codes.

The digital frequency synthesizer 1, in which the principle of the range-quartz stabilization is used, allows forming a stable frequency grid with a step up to, the use of which to form a phase shift allows to increase the accuracy of forming a phase shift in the proposed phase shifter.

Thus, the implementation of the phase control unit in the form of a digital synthesizer 1 frequency and the formation of controlling the formation of phase

the shift of clock pulses from the stable output signal of the digital synthesizer 1 frequency allows to increase the accuracy of forming the phase shift of the phase shifter.

Claims (1)

Invention Formula Phaser containing series-connected phase control unit and bandpass filter, switch, shift register and variable frequency divider division, characterized in that in order to increase the accuracy of the phase shift formation, the phase control unit is implemented as a digital frequency synthesizer and entered a code adder and a variable frequency division divider and a gate generator, the second input of which is connected in series To the output of a frequency divider with a variable division factor, the input of which is connected to the inputs of an additional frequency divider with a variable division factor and a bandpass filter, the output of the strobe generator is connected to the control input of the switch, the signal inputs of which are connected to the outputs of the corresponding shift register bits, outputs the switch is connected to: the first inputs of the corresponding bits of the totalizer codes, the second inputs of the corresponding bits of which are the inputs of the code for setting the frequency of the digit ovogo frequency synthesizer, and outputs the code bits of the adder connected to respective control inputs of a digital frequency synthesizer. / on fdb. FIG. 2 Cc frequency control code