SU1184088A1 - Frequency synthesizer - Google Patents

Abstract

A FREQUENCY SYNTHESIZER containing a digit-analog converter connected in series, an adder, a tunable oscillator, a pulse-phase detector, to another input of which a source of reference pulses is connected, and a low-pass filter, as well as a digital frequency detector characterized in that while maintaining a high purity of the spectrum, a switch is connected between the output of the pulse-phase detector and the second adder, the output of the low-pass filter is connected to the input of a digital frequency detector Pa, between the output of which and the digital-analogue converter inputs are connected serially connected register, code comparison element, controlled code converter and register - counter, the other input of which is connected to the output of the frequency set block, and output to the control input of the controlled code converter , the third input of which is connected to the second input of the code comparison element and the digital frequency detector, wherein the control inputs of the digital frequency detector, register, key, register counter and dial block stot connected to respective outputs of control unit, a trigger input connected to the corresponding output frequency set unit. g

Description

The invention relates to radio engineering and can be used in communication systems to form a grid of stable frequencies in the microwave range.

The aim of the invention is to reduce the tuning time while maintaining high purity of the spectrum.

FIG. Figure 1 shows the structural electrical circuit of the proposed frequency synthesizer; FIG. 2 is a structural electrical circuit of a digital frequency synthesizer; Fig. 3 shows a structural electrical circuit of a register and a comparison element of frequency synthesizer codes; Fig. 4 is a structural electrical circuit of a controlled frequency synthesizer code converter; Fig. 5 is a structural electrical circuit of a register of a frequency synthesizer counter; Fig. 6 is a structural electrical circuit of a frequency synthesizer control unit.

The frequency synthesizer contains the source 1 reference pulses, a pulse phase detector 2, an adjustable oscillator 3, an adder 4, a key 5 low pass filter 6, a digital frequency detector 7, a register 8, a code comparison element 9, a Nfbift control 10 code converter, a register counter 11, a digital-to-analog converter 12, a frequency set block 13, a control block 14.

Digital frequency detector 7 contains a summing counter 15, a subtracting counter 16, intermediate registers 17 and 18, Register counter 11 and code comparison element 9 contains additional register 19, the first additional adder 20, the first inverter 21,

Managed converter 10 codes contains the first and second group of elements And 22 and 23, the first group of elements OR 24 and the second additional adder 25, the register-counter 11 contains the third and fourth group of elements And 26 and 27, the second inverter 28, the second group of elements OR 29, additional element OR 30, universal counter 31,

The control unit 14 contains the first, second, third and fourth triggers 32 to 35, respectively, the binary counter 36 and the decoder 37 "

The synthesizer works in the following way.

The frequency of the adjustable oscillator 3 is determined by the signal at the output of the adder 4, the input of which receives two signals: one from the output of converter 12 has a digital analogue that determines the coarse tuning of the adjustable oscillator, the second from the output of key 5, which synchronizes at one of the harmonics of the reference frequency ring 1 pulse phase adjustment. Since the signal at the output of converter 12 is a digital analogue determined by the code arriving at it from register 11, this code completely determines the harmonic of the reference frequency at which synchronism occurs in the system.

, CPU tuning to a different frequency in the proposed device, the following sequence of operations.

Using the frequency set block 13, a code approximately corresponding to the desired frequency is recorded in register counter 11 (the exact code value is not known, since it depends on a number of destabilizing factors affecting the generator and is determined during operation of the device), Simultaneously with by writing the code, a triggering pulse arrives at the control unit 14, which opens the key 5,

The phase locked loop is disabled. At the output of the pulse-phase detector 2, a beating signal of the frequency of the adjustable oscillator .3 occurs with the harmonics of the reference frequency. The initial frequency setting must be made with an accuracy that provides a detuning of less than half of the reference frequency. The cutoff frequency of the filter 6 LOWER frequencies is also chosen equal to half the reference frequency. In such a case, at the output of the low-pass filter 6, there is only a signal with a frequency of beats of the signal of the adjustable oscillator 3 and the harmonic of the reference frequency to which the tuning is made. This frequency is measured by a digital frequency detector 7 and its corresponding code is stored in register 8, the signal at the first output of control unit 14 sets the time interval for digital frequency detector 7, the signal at the second output is a strobe pulse for rewriting the code into register 8, found code value in register 8, which is proportional to the value of the construction, still does not allow compiling it, since it does not contain information about its sign. To determine the sign of the detuning from the fifth output of the control unit 14, a pulse is applied to the counting input of the register-counter 11 and its content is increased by one discrete value. The frequency of the tunable generator 3 changes accordingly, as well as the frequency of the beats, and in the case when the frequency of the adjustable generator is higher than the frequency of the harmonic tuning NIKI, the frequency of the beats increases, otherwise it decreases. adjustments are chosen to be minimal in order to shorten the transient time. Next, a second measurement of the detuning value is made, and in code comparison element 9, a comparison is made with the previously found value stored in the register. generator 3 at the present time, and the code from the digital frequency detector 7, which determines the amount of detuning. Based on these data, digital frequency detector 7 determines the code corresponding to the setting of the adjustable oscillator 3 at the frequency of the selected harmonic. On a pulse from the fourth output of the control unit 14, the found code is written to the register counter 11. Next, the control unit 14 removes the signal from the third output, the key closes and the phase-locked loop begins to operate. The synthesizer works as follows. The beat signal from the output of the low-pass filter 6 is applied to the counting inputs of the counters of the digital frequency detector 7. In the initial state, the counters 15 and 16 are zeroed and forcibly held in this position by a signal from the first output of the control unit 14. This signal controls the operation of the digital frequency detector 7. It sets the time interval for counters 15 and 16, clears them and overwrites the information in intermediate registers 17 and 18. The code in intermediate register 17 corresponds to a positive number, proportional to the detuning value, in intermediate register 18 - to the negative. A positive number code is applied to register 8, a code comparison item 9 and a controlled code converter 10, a negative number code is fed only to a controlled code converter 10. Such an enhancement of the digital frequency detector 7 makes it possible to simplify the controlled converter of 10 codes. At the inputs A of the controlled converter, the code from register-counter 11, corresponding to the frequency at the present moment, is fed to the inputs B, the code corresponding to the detuning. in the form of a positive number (through the first group of elements And 22), or in the form of a negative number (through the second group of elements And 23). The main element of the register register 1 1 is a universal counter 31, which can operate both in the counting mode and in the information receiving mode. When recording information from the controlled converter 10 codes, the code is fed through the third group of elements And 26, and from block 13 of the frequency set through the fourth group of elements 27. The first trigger 32 of the control unit 14 controls the operation of the binary counter 36 and the decoder 37 the third flip-flops 33 and 34 form temporary gates for the first and second frequency measurements, the fourth flip-flop 35 generates a key control signal 5 in the phase locked loop, In the frequency synthesizer, the frequency of the adjustable oscillator is measured, and the bi Nij between its frequency and the desired frequency settings.

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Claims (1)

. A FREQUENCY SYNTHESIZER comprising a digital-to-analog converter, an adder, a tunable generator, a pulse-phase detector, to the other input of which a reference pulse source is connected, and a low-pass filter, as well as a digital frequency detector, characterized in that, in order to reduce the tuning time when maintaining a high spectrum purity, a key is turned on between the output of the pulse-phase detector and the second input of the adder, the output of the low-pass filter is connected to the input of the digital frequency detector, whose output and the digital-to-analog converter inputs include a series-connected register, a code comparison element, a controlled code converter, and a register is a counter, the other input of which is connected to the output of the frequency set block, and the output is connected to the control input of the controlled code converter, the third input of which is connected with the second input of the code comparison element and a digital frequency detector, while the control inputs of the digital frequency detector, register, key, register counter and frequency set block are connected us to respective outputs of control unit, a trigger input connected to the corresponding output frequency set unit.