SU1429300A1 - Shaper of calibrated time intervals - Google Patents

Abstract

The invention relates to a pulse technique and can be used as part of a generator of calibrated time intervals equipment for monitoring and measuring the time parameters of integrated circuits. The aim of the invention is to reduce the discreteness and increase the speed of setting the time shift. The former contains dividers I and 2, phase shifters 3 and 4, low-frequency phase detectors 5 and 6, tunable quartz oscillators 7 and 8, mixers 9, 10, and I, high-frequency phase detector 12, adders 13 constant voltages, adjustable 14 , controlled divider 15, adder 16 output voltages, shaper 17 output voltages, low-frequency generators 18 and 19, counters 21 and 21, RS-flip-flops 22 and 23, exclusion elements 24 and 25, 26 and 27. The use of the exclusion, splitter, and second loop of the phase automatic frequency control to i 150 MHz in the driver of the series-connected exclusion circuits makes it possible to reduce the discreteness of the time shift setting while slightly decreasing the speed of the time shift setting, 1 Il. (L

Description

4 GO

with so

The invention relates to a pulse technique and can be used as part of a generator calibrated with time intervals of equipment for monitoring and measuring time parameters of integrated circuits.

The purpose of the invention is to reduce the discreteness and increase the speed of setting the time shift.

The drawing shows a functional 1 diagram of a calibrator | cal | ovan time intervals.

The calibrator of the calibrated inter-time EJaflOB contains the first and second 2 dividers, the first 3 and second 4 phasers, the first 5 and the second 6 one-time low-frequency detectors, the first 7. And the second 8 tunable quartz oscillators, the first 9, the second 10, the third and mixers, phase Detector 12 high frequency, adder 3 constant voltage, adjustable oscillator 14, controlled deli- tenb 15, adder 16 output voltages - Clear, driver 17 output voltages, first 18 and second 19 generators low frequencies, first 20 and second 21 counters, first 22 and the second 23 RS-triggers, the first 24 and the second-PiPi 25 elements And, the first 26 and second 7 exclusion schemes.

The fourth input of the driver of the calibration time intervals is connected to the second input of the second, 12 27 outputs, the output of which is connected through the first divider 1, the first phase shifter 3, the first phase detector 5, the first tunable crystal oscillator 7 to the first the input of the first mixer 9, the output of which is connected to the second input of the first phase detector 5, the second output of the first overvoltage crystal oscillator 7 is connected to the second input of the first exclusion circuit 26, the output of which is through But the second divider 2, the second phase shifter 4, the second phase detector 6, the second transient quartz oscillator 8 are connected to the first input of the third mixer 11, the input of the controlled divider 15 and the second input of the high-frequency phase detector 12, the output of which is connected through an adder 13 to one hundred and one voltage with the input of a customizable generator 14, the output of which is connected to the first input of the sum

ten

five

0

5 o

five

0

0

five

the output voltage matrix 16 and the first input of the second mixer 10, the second input of which is the second input of the driver, the output of the mixer 10 is connected to the first input of the high-frequency phase detector 12, the second input of the adder 13 is the third input of the driver, the output of the controlled divider 15 is connected With the second input of the adder 16 output voltages, the output of which is connected to the input of the imager 17 output voltages, the output of which is the output of the generator of calibrated time intervals, the second input of the second phase detector 6 is connected to the output of the third mixer 11, the second input of which is connected to the second input of the first mixer 9 and is the first input of the calibrated time interval j and the output of the first low-frequency generator 18 is connected to the first input of the AND 24 element and the first input of the first counter 20, the overflow output which is connected to the R-stroke of the first RS-flip-flop 22, the output of which is connected to the second input of the first element AND 24, the output of which is connected to the first input of the first exclusion circuit 26, the output of the second generator 19 of low frequency This is connected to the first input of the second element AND 25 and the first input of the second counter 21, the overflow output of which is connected to the R input of the second RS-. the trigger 23, the output of which is connected to the second input of the second element AND 25, the output of which is connected to the first input of the second exclusion circuit 27, the S inputs of the first 22 and second RS 23 flip-flops are the fifth and sixth driver inputs, and the pre-recording inputs The first 20 and second 21 counters are the seventh and eighth inputs of the calibrated time interval generator, respectively.

The shaper works as follows.

To create calibrated time intervals, we use the method of eliminating pulses from the periodic sequence of the first reference frequency fgi, which is fed to the driver input, and its subsequent division by means of divider 1 by N times. GxeMa 27 exclusion from the pulse train with high frequency

em (does not transmit), the number of K pulses equal to the number of specified low-frequency pulses and incoming ng. its control input from an AND 25 element, as a result of which the sequence of pulses at the output of divider 1, having the frequency fcn / Nj, is shifted in phase by an angle of 2T К / К and in time by the value Do, K / f;

At the first input of the element And 25, pulses come from the low-frequency generator 19, and the second input receives the control I1 "1 pulse from the output of the RS flip-flop 23, the number of pulses, which must be fed to the input 27 of the exception; determined by the information from the control input of the counter 21. After the input of the counter 21 from the generator output 19, the specified number of pulses at the output of the counter 21 shows a transfer pulse that arrives at the R input of the trigger 23 and prohibits the passage of pulses from the output of the low-frequency generator 19 through the element 25. The control signal received at the S input of the trigger 23 permits the passage of pulses from the low-frequency generator 19 through the element 25.

At the same time, the minimum phase and time shifts (discretes) are equal to ol min-amii 1 / GM. The said shift is relative to the sequence of pulses at the output of the analogous frequency divider 1 of the second driver, in which no pulses are received at the control input of the exclusion circuit 27. Thus, an exemplary temporal shift at the repetition rate foi / N can be set. To obtain a small phase discrete, it is necessary to perform exclusion circuits 27 and divider 1 with a large division factor, which in turn leads to a significant reduction in the output frequency, which is prevented from increasing by the limited frequency range used in the circuit 27 and divider 1 of the microcircuits. To increase the frequency range of the output signals and to reduce the time discretion, the phase relationship transfer between the signals using a phase-locked loop (PLL) working on secondary beats is used.

14293004

The PLL system for receiving output frequencies up to 150 MHz includes in csg-: - the first phase-g detector of 5 frequencies. reshaping the .1 quats: th generator 7, and so the first mixer 9. The frequency of the generator 7 is chosen such that the equality

fo, -f. f o./N,

(one)

where the second reference frequency, on, stepping on the first input of the driver;

fj, is the frequency of the tunable. crystal oscillator 7 in hold mode; fc,., - the first reference frequency, the post station on the fourth input - the driver.

The first and second reference frequencies are chosen such that the equality

f ,, / N + 4 ,. -. (2)

In the hold mode of the PLL, the phase changes at the input of the phase detector 5 are transmitted to the output of a tunable crystal oscillator 7, the time and phase discretes at the output of the tunable quartz generator 7, respectively

-1-s -r

vP M «n y

(3)

 As follows from the formula (3), dn i of the temporal discretization, given at the frequency f ;, it is necessary

increase the ratio N of the reference frequency ft, i.e. reduce the frequency at which the phase detector works, and on which the frequency adjustment frequency of the tunable quartz oscillator 7 depends, and this in turn leads to a decrease in the speed of setting the time shift.

To reduce the discreteness and increase the speed of the time shift setting, the second PLL loop is used, which is connected to the output of the tunable crystal oscillator 7 via an exception circuit 26, divider 2 and phase shifter 4. The second PLL loop up to 150 MHz contains the second phase detector 6, the second tunable crystal oscillator 8, the third mixer 11. The signal from the output of the generator 7 accesses the circuit 26

and then through the divider 2 "facTOTbi by Nj times and the phase shifter 4 to the input of the phase detector 6. If the Ca input of the control exclusion circuit 26 does not arrive, then a shift ihaM defined by the expression (3) and specified on the code of the tunable | welded reHepatopa 7 at frequency IY correspond to phase and time-discretes

2 /,

YY:

fr

mtsts

(four)

received at the output of the divider 2 at the frequency f / N2,

: In the mode of holding the PLL loop, the phase change at the inputs of the phase detector 20 of the torus 6 is transmitted to the output of the tunable quartz oscillator 8, Time T, " and phase 1p, the detection disk 1, time and phase | the shifts at the output of the tunable generator 8 are respectively

25

| g

.YGG

TO

2T

NTiJl

to,

 commune 1 25ГК

(five)

35

As a result, the time discrete decreases in, a — the stdiness of the time shift task decreases insignificantly because the frequency at which the phase detector 6 of the second loop works is equal to f; i / N ,, that with f –f ,,; much larger than in the case of using only one PLL loop and a divider with a division factor.

If the control pulses arrive at the control input of only the exception circuit 26 and do not arrive at the control input of the circuit 27, then the time and phase discretes, the time and phase shifts at the output of divider 2 at the frequency f / N are respectively

45

one

f7

(6)

These shifts correspond to the following time and phase discretes, time and phase shifts at the frequency f at the output of the tunable generator 8

2., „„

ten

- 20 25

thirty

35

45

50

55

TO

.2

6

. min

2fK

2G

Nl

 f.-5; -Ch - i; (

The number of pulses arriving at the control input of the exclusion circuit 26 from the AND 24 element is set by the generator 18, the counter 20,

trigger 22 and element 24. At the first input of element 24, pulses are received from the low-frequency generator 18, and the second input receives a control pulse from the output of the RS flip-flop 22, the number of pulses that must be fed to the input of the circuit 26, it determines the information received at the input of the record of the counter 20. After the input of the counter 20 from the output of the generator 18 of a given number of pulses, a transfer pulse appears at the output of the counter 20, which goes to R- trigger input 22 and prohibits the passage of pulses from the output of g 18 generator of low frequency, you through the AND gate 24, Signap upravt laziness supplied to the S-input of flip-flop 22, to permit the passage of low frequency generator 18 pulses through AND gate 24.

For lower output frequencies, a frequency divider 15 is used with a variable division factor. The time sampling at the same time retains its value.

The PLL dps arrival frequency of up to 3 Hz includes a high-frequency phase detector 12, a tunable generator 14, a mixer 10, a constant voltage adder 13,

The third reference frequency foj, which arrives at the second input of the calibrator of time intervals, is defined by the expression foj m-fg, where, 3,4 ,, .. (t is an integer number indicating the number of harmonics). The frequency of the tunable oscillator 14 is chosen equal to

 fj t. G „, + G,. (8)

In the hold mode of the PLL, the phase changes at the output of the high-frequency phase detector 12 are transmitted to the output of the tunable oscillator 14,

Temporal T, „y and phase ffjvji, discretes, temporal TJ3, and phase

 The shifts corresponding to the expression (5), the output of the tunable generator 14 are

%

one

 T, Tytl to

2dgk

 -

 -) zmin m N7

P ----- About a

Whose N, N, f, -ib about:

PLL RADOR. Thus, using additionally in the shaper of the calibrated (9) time intervals of the series-connected exclusion schemes, the Time T and Phase Lfg of the divider and the second PLL loop (up to)

discretes, temporal TJ- and fazsevy 50 MHz allowed to reduce discrete S -f J shifts, corresponding to the expression for specifying the time shift in N (7), the output of the tunable generator 14 is

times with a slight decrease in the speed of the job temporary

F, - 21G.

№, m 1 21ГК

-to;

(ten)

Calibrator of calibrated time intervals containing sequentially connected first divider, first phase shifter, first phase. a low-frequency detector, the first iicp-stv. quartz oscillator and the first mixer, the output of which is

To obtain different output frequencies, a constant voltage is given to the third input of the driver, by changing which the frequency of the generator 14 is tuned, taking into account the second input of the first phase requirement (8). first detector

To combine the signals at the output mixer, it is connected to the first input

du serves as a 16 output adder on a calibrator of calibrated intervals.

time, allowing the passage of time, as well as consistent output signal of the desired frequency. Phase-coupled phase detector is a high-voltage 17 output voltage, a constant voltage adder, a tunable generator, the output of which is connected to the first input of the output voltage adder, and an error setting of the calibrated gg, the first input of the mixer, the second temporary input The shifts are uniquely determined; the second input is formed by the error of setting the phase spacer of the calibrated intervals.

shifts, which, in turn, over time, the output of the second mixer depends only on cross-connects with the first input of the phase de-interwave and on the accuracy of the high-40 tector of the high frequency, the second phase input by the PLL which is connected to the input of the control device, supplied to us by the divider, the output of which is connected to the second input of the adder of the output voltages, the output of which is connected to form a short pulse signal from the sinusoidal one.

entrances to mixers, provide isolation between channels up to 80-100 dB,

which leads to a time error of 45 input shaper output

no more than 0.01% of the period. The accuracy of the phase adjustment depends on the stability of the oscillator frequency and the holding band 5, the PLL system.

.)

where ft, is the phase difference at the point of stable equilibrium; yts- initial detuning.

50

voltages, the output of which is the output of a calibrator of time intervals, the second input of a cytmator of direct voltage is the third input of a generator of calibrated time intervals, which is so as to reduce the discreteness and. Neither the speed of setting the time-instability of the frequencies of the gg shift generators, two genera introduced into it, leads to a change in the initial low-frequency drive, two counters,

D, which in turn results in two RS-flip-flops, two AND, two leads to instability of the temporary exclusion schemes, the second phase shifter, the second phase detector, second 1429 3008

a.T Af / a) arcsin S7 th "/ ,.

where l) is the frequency of the adjustable genus of setting the time shift in

times with a slight decrease in the speed of the job temporary

shear.

Claims (1)

Invention Formula A calibrator of calibrated time intervals containing sequentially connected first divider, first phase shifter, first low frequency phase detector, first ic-quart oscillator and the first mixer, whose output is dinene with the second input of the first phase detector, the second input of the first 50 gg swarm tunable crystal oscillator, third mixer, second divider whose output is through a second phase shifter connected in series, a second phase detector connected to the input of a second tunable quartz oscillator, the output of which is connected to the input of a control divider; (mixer, the output of which is connected to the second input of the second phase detector, the second input of the third mixer is connected to the second input of the first mixer, the first code of the first low frequency generator is connected to the first the first input of the first element And the first input of the first counter, the overflow output of which is connected to the R input of the first lRS trigger, the output of which is connected to the second input of the first And element, whose output 1 is connected to the first input of the first exclusion circuit, the output of which is connected to the input the second divider, the second output of the first neipecTpa-connected quartz oscillator is connected to the second input of the first exclusion circuit, the output of the second low-frequency generator is connected to the first input of the second element And and the first input of the second counter, output n The overflow is connected to the E-input of the second An RS flip-flop, the output of which is connected to the second input of the second element I, the output of which is connected to the first input of the second exclusion circuit, the output of which is connected to the input of the first divider, the second input of the second exclusion circuit is the fourth input of the calibrator of time slots, the S inputs of the first and second RS flip-flops are fifth and the sixth inputs, and the preliminary recording inputs of the first and second counters are the seventh and eighth inputs of the calibrator of time slots.