SU1483634A1 - Frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and m. used in devices for frequency stabilization of receiving and transmitting equipment. The purpose of the invention is to increase the spectral purity of the output oscillations at a speed equal to one adjustment interval. The frequency synthesizer contains the reference gr. 1, pulse formers 2 and 6, tunable gr. 4, the frequency divider 5 with a variable coefficient. division, frequency code sensor 7, a pulse-phase detector 3, which includes gr.8 sawtooth voltage, key 9 and memory element 10. To achieve the goal, two elements were entered: AND 11, 12, pulse shaper 13 OR 14 and counter 15. The frequency synthesizer allows tuning speeds from one frequency to another close to the limit by reducing the inertia of the pulse-phase detector in a transient mode and at the same time provides high suppression of the comparison frequency in the output spectrum. 1 il.

Description

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The invention relates to radio engineering and can be used in devices for stabilizing the frequency of radio receiving and radio transmitting equipment.

The aim of the invention is to increase the spectral purity of the output oscillations with a response time equal to one adjustment interval.

The drawing shows a structural electrical circuit of a frequency synthesizer.

The frequency synthesizer contains a reference oscillator 1, the first pulse shaper 2, a pulse-phase detector (IFD) 3, a tunable oscillator 4, a frequency divider 5 with a variable division factor (DFD),, the second shaper 6 pulses, a frequency code sensor 7, a sawtooth 8 generator voltage (GPN), key 9, memory element 10, first element

And 11, the second element And 12, the third driver 13 pulses, the element OR 14, the counter 15.

The frequency synthesizer works as follows.

The frequency of the tunable generator 4 is divided by the PDCD 5 and is compared with the frequency of the reference generator 1 in the IFD 3. The reference frequency signal is fed to the first input of the IFD 3 from the output of the first driver 2. The voltage of the error signal from the output of the IFD 3 is used to stabilize the frequency of the tunable generator 4. You set the output frequency by a command from the sensor 7 of the code, which changes the division ratio of the DPCD 5, and during the transition process the impulses from the second generator 6 will exit to the control key 9 of the IFD 3 n elnost which greatly exceeds the duration of the pulses arriving at the 9 key input from the third control shaper 13 in a stationary state. Counter 15 determines the time required to tune the frequency synthesizer to the new frequency, and at the beginning of the tune from the second output of the sensor 7 of the code, a pulse is written to it equal to the number of adjustment periods required for the tune (usually chosen from theory or practice).

The output of the counter 15 to the second input of the first element And 11 and to the first input of the second element And 12 sends a signal 1, therefore the pulses from the output of the PDCD 5 are fed to the input of the counter 15 working for subtraction, and the pulses from the second imager 6 control the operation of the key 9.

At the output of the counter 15, after reading the number recorded in it, the level O appears, and the counter 15 is blocked until a new pulse is detected at the second output of the sensor 7 of the code.

8 stationary state through the element OR 14 to the input control key

9 only narrower pulses are passed from the output of the third generator 13. In the transient state, the inputs of the OR 14 element simultaneously receive pulses from the outputs of the second and third formers 6 and 13. Since the pulses from the second generator

6 have a longer duration, they determine the closure time of the key 9. The duration of these pulses is selected from the condition of the minimum inertia of the IFD 3, which is determined by the charge rate of the memory element 10. The implementation of the low inertia IFD 3 makes it possible to significantly reduce the time of the transient process. At the end of the transition process on the key 9. pulses come from the third driver 13, the duration of which is chosen from the conditions of the required suppression of the comparison frequency in the output signal spectrum, and it should be done as little as possible.

The minimum possible duration of the pulses of the third imaging unit 13 depends on the parameters of the key 9 (on / off speed, open resistance), the capacity of the memory element 10, as well as the magnitude and rate of change of destabilizing factors affecting the frequency synthesizer.

IFD 3 types of sampling - memorization consists of sequentially included GPN 8, key 9 and memory element 10.

The frequency synthesizer allows you to get the tuning rate from one frequency to another, close to the limit, by reducing the inertia of the pulse-phase detector in a transient mode and at the same time provides a high suppression of the frequency of comparison in the output signal spectrum.

Claims (1)

Invention Formula A frequency synthesizer containing. a series-connected reference generator and a first pulse shaper, a pulse-phase detector connected in series, a tunable generator, a variable dividers frequency divider, and a second pulse shaper, as well as a frequency code sensor, the first output of which is connected to a variable Factor splitter input division, and between the first input and the output of the pulse-phase detector, connected in series are a generator of a sawtooth voltage, a switch and ment memory, the second input key  is a second input of a pulse-phase detector, characterized in that, in order to increase the spectral purity of the output k 0 5 0 at a speed equal to one adjustment interval, between the output of the frequency divider with a variable division factor and the second input of the pulse-phase detector, the first connected And, the counter, the second And and the OR elements are entered, as well as the third pulse shaper, the input and the output of which is respectively connected to the output of a frequency divider with a variable division factor and the second input of the OR element, the output of the second pulse shaper is connected to the second input of the second element nA And, the recording input and the output of the counter are connected respectively to the second output of the frequency code sensor and the second input of the first element I, and the output of the first pulse shaper is connected to the first input of the pulse-phase detector.