SU1146800A2 - Digital frequency synthesizer - Google Patents

Abstract

DIGITAL SYNTHESIZER OF FREQUENCIES according to author. St. No. 1077057, characterized in that, in order to improve speed, the third and fourth single vibrators are introduced into it, the output of the first D-flip-flop is connected to the first input of the first element AND through the additionally introduced first element of the OR, the output of the second D-flip-flop is connected to the first input of the second element And through the additionally introduced second element OR, while the input of the third single vibrator is combined with the R input of the first D flip-flop, and the output of the third single vibrator is connected to the second input of the first OR element, the input of the fourth single vibrator bedinen with R-input of the second D-flip-flop, and a fourth monostable output is connected to a second input of the second OR gate. (L 4 O5 00

Description

The invention relates to radio engineering, and can be used, for example, to generate a frequency grid in transceiver and instrumentation equipment.

According to the main author. St. No. 1077057 discloses a digital frequency synthesizer comprising a series-connected controlled oscillator, a frequency divider with a variable division factor and a frequency phase detector, serially connected a reference oscillator, and a frequency divider with a fixed division factor, the output of which is connected to another input of the frequency-phase detector, the first current generator, the first current switch and the low-pass filter, the output of which is connected to the input of the controlled oscillator, and the successor The connected second generator of current and second current switch, the output of which is also connected to the input of the low-pass filter, between 1: output of the frequency-phase detector and the control input of the first current switch, are connected in series the first strobing unit, the first D-trigger and the first element And, and between the second output of the frequency-phase detector and the control input of the second current key, the second D-trigger and the second And element are serially connected to the second gating unit, and the first and The first one-shot, while the first one-shot is connected between the output of the first D-flip-flop and the D-BXO of the second D-flip-flop, and the second one-shot is connected between the second D-flip-flop and the D-input of the first D-flip-flop; the input of the second gating unit and R the input of the first D-flip-flop, the output of a frequency divider with a variable division factor, is connected to the second input of the first gating unit and to the R-input of the second D-flip-flop, the first and second outputs of the frequency-phase g The detectors are connected respectively to the second inputs of the first and second I elements, and the outputs of the first and second gating units are connected respectively to the installation inputs of a frequency divider with a fixed division factor and a frequency divider with a variable division factor. In this case, the gating unit consists of a series-connected delay element, an OR-NOT element and an AND element, the other input of the OR element is NOT combined with the input of the delay element and is the first input of the gating unit, and the other input and output of the AND element are respectively the second , the input and output of the gating unit (1. However, the well-known digital frequency synthesizer has insufficient speed

Because when switching from frequency to frequency, a pulse at the output of the gating unit is formed only when the phase difference between the pulses from the output of the dividers with variable and fixed division factors is greater than the delay dC at the delay element. That is, the impact on the current key and the reset of the dividers to the initial state is not carried out in the whole range of detuning, which reduces the speed.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that in a digital frequency synthesizer, which contains a series-connected controlled oscillator, a frequency divider with a variable division factor and a frequency-phase detector, a series-connected reference oscillator and a frequency divider with a fixed division factor, the output of which is connected to another input of the frequency-phase detector, serially connected first current generator, first current switch and low-pass filter, the output of which is connected to the input of the controlled generator, and edovatelno connected to the second current generator and a second current switch whose output is also connected to the input of a low pass filter between a first output of the phase frequency detector and the control input of the first current

The 0 key is connected in series with the first gating unit, the first D TpH-ger and the first And element, and between the second output of the frequency-phase detector and the control input of the second current key, the consistently connected second gating unit, the second D-trigger and the second And element are inserted, and the first and second single vibrators are also introduced, the first single vibrator being connected between the output of the first D-flip-flop and the D input of the second D-flip-flop, and the second single vibrator is connected between the output of the second D-flip-flop and the D input of the first b-flip-flop, the output of the frequency divider with a fixed division factor is connected to the second input of the second gating unit and the R input of the first D-flip-flop; the output of the frequency divider with a variable division factor is connected to the second input of the first gating unit and to the R input of the second D-flip-flop, the first and , the second outputs of the frequency-phase detector

0 are connected respectively to the second inputs of the first and second I elements, and the outputs of the first and second gating units are connected respectively to the installation inputs of a frequency divider with a fixed division factor and a frequency divider with a variable division factor, the gating unit consisting of successively connected delay elements, an OR-NOT element and an AND element, the other input of the OR-NOT element is combined with the input of the delay element and is the first input of the gating unit, and the other input and output of the element This And are the second input and output of the gating unit, the third and fourth one-shot are entered, the output of the first D-flip-flop is connected to the first input of the first element AND through the additionally introduced first element OR, the output of the second D-flip-flop is connected to the first input of the second element And additionally introduced a second element OR, while the input of the third one-shot is combined with the R-input of the first D-flip-flop, and the output of the third one-shot is connected to the second input of the first element OR, the input of the fourth one-fold The ora is combined with the R-input of the second D-flip-flop, and the output of the fourth one-shot is connected to the second input of the second OR element. The drawing shows the structural scheme of the proposed digital frequency synthesizer. The digital frequency synthesizer contains a controlled oscillator 1, a frequency divider with a variable division factor (DPDK) 2, a frequency-phase detector (FFD) 3, a reference oscillator 4, a divider with a fixed division factor (DFCD) 5, the first gating unit 6, the second block 7 gating, the first D-flip-flop 8, the second D-flip-flop 9, the first one-shot 10, the second one-shot 11, the third one-shot 12, the fourth one-shot 13, the first element OR 14, the second element OR 15, the first element AND 16, the second element. ment 17, the first current switch 18, the second current switch 19, the first current generator 20, the second current generator 21, the low-pass filter 22 (LPF), the delay element 23, the element OR NOT 24 and the element 25. The digital frequency synthesizer. works as follows. In the synchronism mode, short pulses are formed at the output of the FPD 3, which almost coincide with each other in time. These pulses pass through the first element 16 and 16 to the first current switch 18, respectively, and through the second element 17 to the second current switch 19. The current switches 18 and 19 open for a short time and carry out almost simultaneous charge-discharge of the low-pass filter. 22 so that the control voltage equal to the output voltage of the low-pass filter 22 is almost unchanged. At the same time, the pulses from the outputs of the PFD 3 are fed to the first inputs of the first and second blocks 6 and 7 of the gating. Since the phase difference df of pulses at the inputs of the FFD 3 in synchronism mode is less than the delay value in gating blocks 6 and 7, there are no gates from the outputs of gating blocks 6 and 7 at the C inputs of D flip-flops 8 and 9. At the same time, the input of the third one-shot and the R-input of the first D-flip-flop 8 receives pulses from DFCD 5, which set the first D-flip-flop 8 to the “Log. 1. This potential prevents the passage of extended-duration pulses from the output of the third one-shot 12 through the first input of the first element OR 14 to the second input of the first element 16. At the same time, the potential “Log. 1 at the output of the first element OR 14 permits the passage of pulses from the PFD 3 through the first element AND 16 to the control input of the first current switch 18. When switching to a different frequency, the pulses from the DPKD 2 and DFCD 5 do not coincide with each other in time. AT . As a result, pulses with a duration equal to the phase difference of these signals are formed at one of the outputs of the PED 3; Pulses with a duration equal to the phase difference arrive at the inputs of the ILINE 24 element directly and through the delay element 23. If the phase difference exceeds the delay value C of the delay element 23, then the output of the OR-NOT 24 element generates a pulse equal in duration to t 4 (p-dyag, which permits a short pulse passing through the AND 25 element with DPDC 2. This pulse arrives at The C input of the first D flip-flop 8 and the reset input of the DFCD 5 set it to the initial state of the account, i.e. in the DCPD 2 and DFCD 5, the counting of pulses starts from the controlled generator 1 and the reference generator 4 simultaneously. arrived at the C-input of the first D-trigger 8, overturning This is because the inhibiting potentials at the D input from the output of the second one-shot 11 usually have several adjustment periods, i.e. the blocking time from the one-shot is short and is set in advance. As a result of the first D trigger 8, a negative pulse is generated at its output, which permits the passage a negative pulse from the output of the third single vibrator 12 through the first element OR 14. The third single vibrator 12 expands the pulses from the DFCD 5 to a certain value, which is chosen from the following zheny. The smallest phase difference at the output of the PED 3, at which the strobe impulse passes from the output of the first gating unit 6, requires the control input of the first current switch 18 to have a pulse longer than the phase difference by some additional value t. but less than the remainder of the adjustment period. The magnitude of the additional time effect 1d is created at the output of the first element OR 14 as the difference between the duration of the negative impulse at the output of the first D-flip-flop 8 and the remaining duration of the positive impulse at the output of the third one-shot 12. As the last is triggered by the impulse with DFCD 5, and the first is DFD trigger 8 - from a pulse with DPKD 2, then, the larger the phase difference, the greater the difference pulse at the output of the first element OR 14, which passes through the first element 16 to the control input of the first current switch 18 and it folds in time with a pulse at the output of the PFD 3. At the maximum phase difference, the control action lasts for the whole period of regulation. With a decrease in the frequency and phase mismatch, the first D-flip-flop 8 is turned off, and the usual regulation takes place in the auto-tuning system. If a small overshoot occurs after the passage of the equilibrium state, the second D-flip-flop 9 cannot be turned on, since it is blocked for some time by the D-input by the inhibitory potential from the output of the first one-shot 10. The first one-shot 10 turns on by a negative pulse from the output of the first D -trigger 8 when it is triggered from a short pulse at the C-input. The digital frequency synthesizer works in the same way if the period of pulses from DPKD 2 is less than the period of pulses from DFCD 5. Only in this case the DPKD 2 is reset using pulses from DFCD 5 passing through the second gating unit 7. Thus, in the proposed digital frequency synthesizer, after strobe-pulse extraction from gating blocks 6 and 7, the shaped effect on the control inputs of the current switches 18 and 19 can vary depending on the initial phase difference from the minimum possible to the maximum equal to the entire adjustment period. This significantly reduces the possibility of overshoot.

Claims (1)

DIGITAL FREQUENCY SYNTHESIS by auth. St. No. 1077057, characterized in that, in order to improve performance, a third and fourth one-shot are introduced into it, the output of the first D-trigger is connected to the first input of the first element And through the additionally introduced first element OR, the output of the second D-trigger is connected to the first input of the second AND element through an additionally introduced second OR element, wherein the input of the third one-shot is combined with the R-input of the first D-trigger, and the output of the third one-shot is connected to the second input of the first OR, the input of the fourth one-shot nen with the R-input of the second D-flip-flop, and the output of the fourth one-shot is connected to the second input of the second OR element.