SU1506552A2 - Frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and can be used to generate a frequency grid in broadband transmitting and receiving devices. The purpose of the invention is to expand the range of continuous frequency tuning. To achieve the goal, the key 27, the IS-28 multi-input element 28, the counter 29, the inverter 30 and their distinctive connections are entered into the frequency synthesizer. Continuous tuning is performed over the entire operating frequency range. The error in setting the new control voltage is small and is being processed by the PLL circuit. The range of continuous frequency tuning is equal to the entire working frequency range and expands to (F _max -F _min ) / S ₁ ^. S ₂ (T ₀ -1 / F _min ) times, where F _max , F _min - max. and min. frequency of the operating frequency range, S ₁ is equivalent to the steepness of the control controlled by the generator 7, S ₂ is equivalent to the steepness of the x-ki conversion of the phase detector 3, T ₀ is the period of the frequency of the comparison at the output of the detector 3. 1

Description

cl

about

O5

cl

O1 1C

hch

315

The invention relates to radio engineering and can be used to generate a frequency grid in wide. radio transmitters and receivers, and is an improvement of the invention according to Aut., No. 1385293.

The purpose of the invention is to expand the range of continuous frequency tuning.

The drawing shows a structural electrical circuit of a frequency synthesizer.

The frequency synthesizer contains a reference oscillator 1, a frequency divider 2 with a fixed division factor (DFCD), a phase detector 3, the first stable current generator 4 (GST), the second GTS 5, a low-pass filter 6, a controlled oscillator 7 divider 8 variable division frequency (DFD) frequencies, code converter 9, code sensor 10, first key 11, shift register 12, second key 13, first inverter 14, third key 15, RS flip-flop 16, first AND-OR element 17, second the element AND-OR 18, the element 19 delay, the first element OR 20, the second element OR 21, formed the pulse pulley 22, the first storage unit 23, the intermediate division factor calculation unit 24, the switching unit 25, the second storage unit 26, the fourth key 27, the AND-H 28, multi-input element, the counter 29 and the second inverter 30.

The frequency synthesizer works as follows.

In its initial state, the controlled oscillator 7 generates a signal with a frequency f defined by the division factor N, DPCD 8 and due to the operation of the phase locked loop, which also includes phase detector 3, the first and second GST 4 and 5, the filter 6, the first and second elements are AND-OR 17 and 18, the reference generator 1 and the DFCD 2. The pulse sequences at the inputs of the phase detector 3 have the same repetition period and zero phase shift. At the first control input of the converter 9 of the code, the signal is absent and the code inputs of the DDCD 8 through the converter 9 of the code arrive without changing the frequency code f, from the output of the sensor 10 of the code. After completing a set of new values

Q

5 0 5 0 s

Q

five

The frequency f, 2 at the installation output of the sensor 10 of the code appears impulse installation and at the code outputs of the sensor 10 of the code there is information about the new value of the frequency f. The impulse of the installation is fed to the second control input of the code converter 9, which processes codes. At its first information output, either a Log.O level or a Log.1 level is established, depending on the sign of the frequency difference. A code number n equal to the number of additional comparison frequency periods at the input of the phase detector 3 required for continuous tuning in the frequency range.

The output of the RS flip-flop 16 sets a level of Log, 1, under the action of which an intermediate dividing coefficient code appears at the code outputs of the code converter 9, proportional to the difference between the previous frequency value f, and the new value f., Setting pulse through delay element 19, delayed by the time of forming the code Nnp, is fed to the input of zeroing DFCD 2, to the input of the second element OR 21, and through the first element OR 20 to the input of zeroing DCPD B. Both frequency dividers are zeroed and the signal from the output of the former 22 dividing ratio setting descends DPKD 8 Npn.

The intermediate division cycle begins, which is necessary for the pulses from the DFCD 2 and DCD 8 outputs to appear at the inputs of the phase detector 3 in sequence and with the delay necessary for the new voltage value corresponding to the set frequency f2 to form the phase detector 3.

The pulse sequence at the inputs of the phase detector 3 and the delay time are determined by the sign and magnitude of the detuning. Depending on the mismatch sign using the second key 13 of the inverter 14, the first and second AND-OR elements 17 and 18, the inputs of the phase detector 3 are connected either to the output of the PDD 8 or to the output of the DCDD 2. The inputs of the phase detector 3 are connected via the signal Log .1 from the first output of register 12 when a pulse is applied to the input of the first key 11. By the signal Log. From the output of the second inverter 30, the counter 29 switches to the counting mode with a capacitance n. At the output of the multi-input element IS-NOT 28, in the case of p, the level Log.O is set and the fourth key 27 is closed.

With the appearance of a pulse at the DCDD 8 output, the second output of the register 12 appears at the level of Log.1, which blocks the DCD 8. At the outputs of the code converter 9, the code N appears, corresponding to the new frequency value f. When a 2-th pulse appears at the DFCD output, a signal of Log.1 appears at the output of the IS-NE 28 multi-input element and the fourth key 27 opens. Depending on the mismatch sign, either the next or the second inputs of the phase detector 3 and simultaneously to the first input of the third key 15, the next pulse from the DFCD 2 output is recorded. Information about the new frequency f in the 9 code converter is recorded at its output. Simultaneously with this, the lock from DPCD 8 is removed, its division factor is set to N and a new division cycle begins.

Switching unit 25 is used to connect to the code outputs of the converter 8 codes or the frequency code from the output of code 10, or the intermediate dividing coefficient code N p from the output of computing unit 24, which processes codes from the output of code sensor 10 and the first storage unit 23. At the first information output of the calculator 24, information about the rearrangement sign appears. The first storage unit 23 is used to record information about the new frequency f on the signal received at the third control input of the code converter 9, and store this information for calculating the intermediate division factor.

The second storage unit 26 serves to record the control characteristic f LP (and) of the controlled oscillator 7 and the conversion characteristic and If (t) of the phase detector 3.

The operation algorithm of the calculation unit 24 is described by the following expression:

N .. (n 0-j |, 5y-iNo-N .I

 N, (-s; rs Tj-);

where T is the period of the comparison frequency at the output of the phase detector 3i

 - is equivalent to the steepness of the control controlled by the generator 7.

The values of U and U are determined from the control characteristic I stored in the second memory block 26.

f (i); S,, is the equivalent of | ti2-t, |

on the steepness of the conversion characteristic of the phase detector 3.

The values of t- and t are determined by the conversion characteristic (t) recorded in the second memory block 26, n is the number of additional comparison periods Tjj at the input of the phase detector 3 needed for continuous tuning in the frequency range.

The maximum duration of continuous adjustment P is found from the condition N i p. min

40

., - / - IfLif- ..)

 A.aKc-i S, S /

mox

45

In the worst case, f, f mon “and the frequency of the working frequency range is minimal

- -fi; r

Duration Ut dr „, additional

t

"Lacquer

until period t

  0 mox

f HUH

n is defined as an integral part of the expression

   + -I,.

S, S

t

1 o

f t

-ALIN -o

The sign of the adjustment is determined by the sign of the difference

,

Nilni

In the frequency synthesizer, continuous tuning is performed over the entire operating frequency range. The error in setting the new control voltage is not significant and is being processed by a phase locked loop. The range of continuous frequency tuning is equal to the entire working frequency range and expands to

.f jS2S.-Zlj il -

ST Si (Te-7)

 / min

time,

where fwoKc is the maximum frequency

working frequency range.

Claims (1)

Invention Formula Frequency Synthesizer for auth. No. 1385293, I distinguish y with the fact that, in order to expand the range of continuous frequency tuning, the second inverter, the counter and the multi-input element AND-NOT are entered in series, the first inputs of the first and second AND-OR elements, the first input of the third key are connected to the output of the frequency divider with a fixed division factor through the additionally introduced fourth key, the second input of which is connected with the output of the multi-input element I-YE, the input of the second inverter is connected to the first output of the shift register, the counting and information inputs of the counter are connected respectively to the output of a frequency divider with a fixed division factor and the second information output of the code converter, while the second information output of the code converter is the second information output of the block calculating an intermediate division factor.